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GET /api/patches/79702/?format=api
{ "id": 79702, "url": "http://patches.dpdk.org/api/patches/79702/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20201005184526.7465-12-konstantin.ananyev@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20201005184526.7465-12-konstantin.ananyev@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20201005184526.7465-12-konstantin.ananyev@intel.com", "date": "2020-10-05T18:45:23", "name": "[v3,11/14] acl: for AVX512 classify use 4B load whenever possible", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "37f83e8acd9f1288974c3a698832a0d097e92d52", "submitter": { "id": 33, "url": "http://patches.dpdk.org/api/people/33/?format=api", "name": "Ananyev, Konstantin", "email": "konstantin.ananyev@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20201005184526.7465-12-konstantin.ananyev@intel.com/mbox/", "series": [ { "id": 12702, "url": "http://patches.dpdk.org/api/series/12702/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12702", "date": "2020-10-05T18:45:21", "name": "acl: introduce AVX512 classify methods", "version": 3, "mbox": "http://patches.dpdk.org/series/12702/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/79702/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/79702/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 12A2BA04B1;\n\tMon, 5 Oct 2020 21:43:14 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3F10F1B3E7;\n\tMon, 5 Oct 2020 21:43:12 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id 972192952\n for <dev@dpdk.org>; Mon, 5 Oct 2020 21:43:10 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 Oct 2020 12:28:12 -0700", "from sivswdev08.ir.intel.com ([10.237.217.47])\n by orsmga005.jf.intel.com with ESMTP; 05 Oct 2020 11:46:43 -0700" ], "IronPort-SDR": [ "\n 6+NPfSd4H4jyvQTVXAEHU51o89+nOiE7YOrhVi8IT9AkphwVvPPpKI9FVSLo+93noUdEMw6GBZ\n NhSDoIUoFyKg==", "\n dEDSZHpXwbvApAReug9JT1LwGwi2qkaIAjp0JVXDi3ht101yKEvCMY/GvYvLPX2ubjoVL+X51/\n dlFK8F97fOVw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9765\"; a=\"143299570\"", "E=Sophos;i=\"5.77,340,1596524400\"; d=\"scan'208\";a=\"143299570\"", "E=Sophos;i=\"5.77,340,1596524400\"; d=\"scan'208\";a=\"526625933\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Konstantin Ananyev <konstantin.ananyev@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, ruifeng.wang@arm.com, vladimir.medvedkin@intel.com,\n Konstantin Ananyev <konstantin.ananyev@intel.com>", "Date": "Mon, 5 Oct 2020 19:45:23 +0100", "Message-Id": "<20201005184526.7465-12-konstantin.ananyev@intel.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20201005184526.7465-1-konstantin.ananyev@intel.com>", "References": "<20200915165025.543-1-konstantin.ananyev@intel.com>\n <20201005184526.7465-1-konstantin.ananyev@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 11/14] acl: for AVX512 classify use 4B load\n\twhenever possible", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "With current ACL implementation first field in the rule definition\nhas always to be one byte long. Though for optimising classify\nimplementation it might be useful to do 4B reads\n(as we do for rest of the fields).\nSo at build phase, check user provided field definitions to determine\nis it safe to do 4B loads for first ACL field.\nThen at run-time this information can be used to choose classify\nbehavior.\n\nSigned-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n lib/librte_acl/acl.h | 1 +\n lib/librte_acl/acl_bld.c | 34 ++++++++++++++++++++++++++++++\n lib/librte_acl/acl_run_avx512.c | 2 ++\n lib/librte_acl/acl_run_avx512x16.h | 8 +++----\n lib/librte_acl/acl_run_avx512x8.h | 8 +++----\n lib/librte_acl/rte_acl.c | 1 +\n 6 files changed, 46 insertions(+), 8 deletions(-)", "diff": "diff --git a/lib/librte_acl/acl.h b/lib/librte_acl/acl.h\nindex 7ac0d12f08..4089ab2a04 100644\n--- a/lib/librte_acl/acl.h\n+++ b/lib/librte_acl/acl.h\n@@ -169,6 +169,7 @@ struct rte_acl_ctx {\n \tint32_t socket_id;\n \t/** Socket ID to allocate memory from. */\n \tenum rte_acl_classify_alg alg;\n+\tuint32_t first_load_sz;\n \tvoid *rules;\n \tuint32_t max_rules;\n \tuint32_t rule_sz;\ndiff --git a/lib/librte_acl/acl_bld.c b/lib/librte_acl/acl_bld.c\nindex d1f920b09c..da10864cd8 100644\n--- a/lib/librte_acl/acl_bld.c\n+++ b/lib/librte_acl/acl_bld.c\n@@ -1581,6 +1581,37 @@ acl_check_bld_param(struct rte_acl_ctx *ctx, const struct rte_acl_config *cfg)\n \treturn 0;\n }\n \n+/*\n+ * With current ACL implementation first field in the rule definition\n+ * has always to be one byte long. Though for optimising *classify*\n+ * implementation it might be useful to be able to use 4B reads\n+ * (as we do for rest of the fields).\n+ * This function checks input config to determine is it safe to do 4B\n+ * loads for first ACL field. For that we need to make sure that\n+ * first field in our rule definition doesn't have the biggest offset,\n+ * i.e. we still do have other fields located after the first one.\n+ * Contrary if first field has the largest offset, then it means\n+ * first field can occupy the very last byte in the input data buffer,\n+ * and we have to do single byte load for it.\n+ */\n+static uint32_t\n+get_first_load_size(const struct rte_acl_config *cfg)\n+{\n+\tuint32_t i, max_ofs, ofs;\n+\n+\tofs = 0;\n+\tmax_ofs = 0;\n+\n+\tfor (i = 0; i != cfg->num_fields; i++) {\n+\t\tif (cfg->defs[i].field_index == 0)\n+\t\t\tofs = cfg->defs[i].offset;\n+\t\telse if (max_ofs < cfg->defs[i].offset)\n+\t\t\tmax_ofs = cfg->defs[i].offset;\n+\t}\n+\n+\treturn (ofs < max_ofs) ? sizeof(uint32_t) : sizeof(uint8_t);\n+}\n+\n int\n rte_acl_build(struct rte_acl_ctx *ctx, const struct rte_acl_config *cfg)\n {\n@@ -1618,6 +1649,9 @@ rte_acl_build(struct rte_acl_ctx *ctx, const struct rte_acl_config *cfg)\n \t\t\t\t/* set data indexes. */\n \t\t\t\tacl_set_data_indexes(ctx);\n \n+\t\t\t\t/* determine can we always do 4B load */\n+\t\t\t\tctx->first_load_sz = get_first_load_size(cfg);\n+\n \t\t\t\t/* copy in build config. */\n \t\t\t\tctx->config = *cfg;\n \t\t\t}\ndiff --git a/lib/librte_acl/acl_run_avx512.c b/lib/librte_acl/acl_run_avx512.c\nindex 74698fa2ea..3fd1e33c3f 100644\n--- a/lib/librte_acl/acl_run_avx512.c\n+++ b/lib/librte_acl/acl_run_avx512.c\n@@ -11,6 +11,7 @@ struct acl_flow_avx512 {\n \tuint32_t num_packets; /* number of packets processed */\n \tuint32_t total_packets; /* max number of packets to process */\n \tuint32_t root_index; /* current root index */\n+\tuint32_t first_load_sz; /* first load size for new packet */\n \tconst uint64_t *trans; /* transition table */\n \tconst uint32_t *data_index; /* input data indexes */\n \tconst uint8_t **idata; /* input data */\n@@ -24,6 +25,7 @@ acl_set_flow_avx512(struct acl_flow_avx512 *flow, const struct rte_acl_ctx *ctx,\n {\n \tflow->num_packets = 0;\n \tflow->total_packets = total_packets;\n+\tflow->first_load_sz = ctx->first_load_sz;\n \tflow->root_index = ctx->trie[trie].root_index;\n \tflow->trans = ctx->trans_table;\n \tflow->data_index = ctx->trie[trie].data_index;\ndiff --git a/lib/librte_acl/acl_run_avx512x16.h b/lib/librte_acl/acl_run_avx512x16.h\nindex 981f8d16da..a39df8f3c0 100644\n--- a/lib/librte_acl/acl_run_avx512x16.h\n+++ b/lib/librte_acl/acl_run_avx512x16.h\n@@ -460,7 +460,7 @@ match_check_process_avx512x16x2(struct acl_flow_avx512 *flow, uint32_t fm[2],\n \n \t\tif (n[0] != 0) {\n \t\t\tinp[0] = get_next_bytes_avx512x16(flow, &pdata[0],\n-\t\t\t\trm[0], &di[0], sizeof(uint8_t));\n+\t\t\t\trm[0], &di[0], flow->first_load_sz);\n \t\t\tfirst_trans16(flow, inp[0], rm[0], &tr_lo[0],\n \t\t\t\t&tr_hi[0]);\n \t\t\trm[0] = _mm512_test_epi32_mask(tr_lo[0],\n@@ -469,7 +469,7 @@ match_check_process_avx512x16x2(struct acl_flow_avx512 *flow, uint32_t fm[2],\n \n \t\tif (n[1] != 0) {\n \t\t\tinp[1] = get_next_bytes_avx512x16(flow, &pdata[2],\n-\t\t\t\trm[1], &di[1], sizeof(uint8_t));\n+\t\t\t\trm[1], &di[1], flow->first_load_sz);\n \t\t\tfirst_trans16(flow, inp[1], rm[1], &tr_lo[1],\n \t\t\t\t&tr_hi[1]);\n \t\t\trm[1] = _mm512_test_epi32_mask(tr_lo[1],\n@@ -494,9 +494,9 @@ search_trie_avx512x16x2(struct acl_flow_avx512 *flow)\n \tstart_flow16(flow, MASK16_BIT, UINT16_MAX, &pdata[2], &idx[1], &di[1]);\n \n \tin[0] = get_next_bytes_avx512x16(flow, &pdata[0], UINT16_MAX, &di[0],\n-\t\t\tsizeof(uint8_t));\n+\t\t\tflow->first_load_sz);\n \tin[1] = get_next_bytes_avx512x16(flow, &pdata[2], UINT16_MAX, &di[1],\n-\t\t\tsizeof(uint8_t));\n+\t\t\tflow->first_load_sz);\n \n \tfirst_trans16(flow, in[0], UINT16_MAX, &tr_lo[0], &tr_hi[0]);\n \tfirst_trans16(flow, in[1], UINT16_MAX, &tr_lo[1], &tr_hi[1]);\ndiff --git a/lib/librte_acl/acl_run_avx512x8.h b/lib/librte_acl/acl_run_avx512x8.h\nindex cfba0299ed..fedd79b9ae 100644\n--- a/lib/librte_acl/acl_run_avx512x8.h\n+++ b/lib/librte_acl/acl_run_avx512x8.h\n@@ -418,7 +418,7 @@ match_check_process_avx512x8x2(struct acl_flow_avx512 *flow, uint32_t fm[2],\n \n \t\tif (n[0] != 0) {\n \t\t\tinp[0] = get_next_bytes_avx512x8(flow, &pdata[0],\n-\t\t\t\trm[0], &di[0], sizeof(uint8_t));\n+\t\t\t\trm[0], &di[0], flow->first_load_sz);\n \t\t\tfirst_trans8(flow, inp[0], rm[0], &tr_lo[0],\n \t\t\t\t&tr_hi[0]);\n \t\t\trm[0] = _mm256_test_epi32_mask(tr_lo[0],\n@@ -427,7 +427,7 @@ match_check_process_avx512x8x2(struct acl_flow_avx512 *flow, uint32_t fm[2],\n \n \t\tif (n[1] != 0) {\n \t\t\tinp[1] = get_next_bytes_avx512x8(flow, &pdata[2],\n-\t\t\t\trm[1], &di[1], sizeof(uint8_t));\n+\t\t\t\trm[1], &di[1], flow->first_load_sz);\n \t\t\tfirst_trans8(flow, inp[1], rm[1], &tr_lo[1],\n \t\t\t\t&tr_hi[1]);\n \t\t\trm[1] = _mm256_test_epi32_mask(tr_lo[1],\n@@ -452,9 +452,9 @@ search_trie_avx512x8x2(struct acl_flow_avx512 *flow)\n \tstart_flow8(flow, MASK8_BIT, UINT8_MAX, &pdata[2], &idx[1], &di[1]);\n \n \tin[0] = get_next_bytes_avx512x8(flow, &pdata[0], UINT8_MAX, &di[0],\n-\t\t\tsizeof(uint8_t));\n+\t\t\tflow->first_load_sz);\n \tin[1] = get_next_bytes_avx512x8(flow, &pdata[2], UINT8_MAX, &di[1],\n-\t\t\tsizeof(uint8_t));\n+\t\t\tflow->first_load_sz);\n \n \tfirst_trans8(flow, in[0], UINT8_MAX, &tr_lo[0], &tr_hi[0]);\n \tfirst_trans8(flow, in[1], UINT8_MAX, &tr_lo[1], &tr_hi[1]);\ndiff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c\nindex 245af672ee..f1474038e5 100644\n--- a/lib/librte_acl/rte_acl.c\n+++ b/lib/librte_acl/rte_acl.c\n@@ -500,6 +500,7 @@ rte_acl_dump(const struct rte_acl_ctx *ctx)\n \tprintf(\"acl context <%s>@%p\\n\", ctx->name, ctx);\n \tprintf(\" socket_id=%\"PRId32\"\\n\", ctx->socket_id);\n \tprintf(\" alg=%\"PRId32\"\\n\", ctx->alg);\n+\tprintf(\" first_load_sz=%\"PRIu32\"\\n\", ctx->first_load_sz);\n \tprintf(\" max_rules=%\"PRIu32\"\\n\", ctx->max_rules);\n \tprintf(\" rule_size=%\"PRIu32\"\\n\", ctx->rule_sz);\n \tprintf(\" num_rules=%\"PRIu32\"\\n\", ctx->num_rules);\n", "prefixes": [ "v3", "11/14" ] }