Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 7940,
    "url": "http://patches.dpdk.org/api/patches/7940/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1445609833-17649-2-git-send-email-david.hunt@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1445609833-17649-2-git-send-email-david.hunt@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1445609833-17649-2-git-send-email-david.hunt@intel.com",
    "date": "2015-10-23T14:17:03",
    "name": "[dpdk-dev,01/11] lib: add armv8 rte_atomic.h",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "6bc8cbf2f9d6a5706ce2396eb6aa3f19790ef80f",
    "submitter": {
        "id": 342,
        "url": "http://patches.dpdk.org/api/people/342/?format=api",
        "name": "Hunt, David",
        "email": "david.hunt@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1445609833-17649-2-git-send-email-david.hunt@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/7940/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/7940/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id CC16D5949;\n\tFri, 23 Oct 2015 16:17:36 +0200 (CEST)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 3CFA15927\n\tfor <dev@dpdk.org>; Fri, 23 Oct 2015 16:17:35 +0200 (CEST)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga102.jf.intel.com with ESMTP; 23 Oct 2015 07:17:33 -0700",
            "from irvmail001.ir.intel.com ([163.33.26.43])\n\tby orsmga003.jf.intel.com with ESMTP; 23 Oct 2015 07:17:32 -0700",
            "from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com\n\t[10.237.217.46])\n\tby irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id\n\tt9NEHVGb002462; Fri, 23 Oct 2015 15:17:31 +0100",
            "from sivswdev02.ir.intel.com (localhost [127.0.0.1])\n\tby sivswdev02.ir.intel.com with ESMTP id t9NEHVJK017700;\n\tFri, 23 Oct 2015 15:17:31 +0100",
            "(from dhunt5@localhost)\n\tby sivswdev02.ir.intel.com with  id t9NEHVmT017696;\n\tFri, 23 Oct 2015 15:17:31 +0100"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.20,186,1444719600\"; d=\"scan'208\";a=\"670321721\"",
        "From": "David Hunt <david.hunt@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Fri, 23 Oct 2015 15:17:03 +0100",
        "Message-Id": "<1445609833-17649-2-git-send-email-david.hunt@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1445609833-17649-1-git-send-email-david.hunt@intel.com>",
        "References": "<1445609833-17649-1-git-send-email-david.hunt@intel.com>",
        "Cc": "Benjamin Boren <Ben.Boren@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 01/11] lib: add armv8 rte_atomic.h",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Benjamin Boren <Ben.Boren@intel.com>\n\nSigned-off-by: Benjamin Boren <Ben.Boren@intel.com>\nSigned-off-by: David Hunt <david.hunt@intel.com>\n---\n .../common/include/arch/arm64/rte_atomic.h         | 269 +++++++++++++++++++++\n 1 file changed, 269 insertions(+)\n create mode 100644 lib/librte_eal/common/include/arch/arm64/rte_atomic.h",
    "diff": "diff --git a/lib/librte_eal/common/include/arch/arm64/rte_atomic.h b/lib/librte_eal/common/include/arch/arm64/rte_atomic.h\nnew file mode 100644\nindex 0000000..c9e0dff\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/arm64/rte_atomic.h\n@@ -0,0 +1,269 @@\n+/*\n+ *   BSD LICENSE\n+ *\n+ *   Copyright(c) 2015 Intel Corporation. All rights reserved.\n+ *\n+ *   Redistribution and use in source and binary forms, with or without\n+ *   modification, are permitted provided that the following conditions\n+ *   are met:\n+ *\n+ *     * Redistributions of source code must retain the above copyright\n+ *       notice, this list of conditions and the following disclaimer.\n+ *     * Redistributions in binary form must reproduce the above copyright\n+ *       notice, this list of conditions and the following disclaimer in\n+ *       the documentation and/or other materials provided with the\n+ *       distribution.\n+ *     * Neither the name of Intel Corporation nor the names of its\n+ *       contributors may be used to endorse or promote products derived\n+ *       from this software without specific prior written permission.\n+ *\n+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ *   \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_ATOMIC_ARM64_H_\n+#define _RTE_ATOMIC_ARM64_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_atomic.h\"\n+\n+/**\n+ * @file\n+ * Atomic Operations\n+ *\n+ * This file defines a API for atomic operations.\n+ */\n+\n+/**\n+ * General memory barrier.\n+ *\n+ * Guarantees that the LOAD and STORE operations generated before the\n+ * barrier occur before the LOAD and STORE operations generated after.\n+ */\n+#define\trte_mb()  {asm volatile(\"dsb sy\" : : : \"memory\"); }\n+\n+/**\n+ * Write memory barrier.\n+ *\n+ * Guarantees that the STORE operations generated before the barrier\n+ * occur before the STORE operations generated after.\n+ */\n+#define\trte_wmb() {asm volatile(\"dsb st\" : : : \"memory\"); }\n+\n+/**\n+ * Read memory barrier.\n+ *\n+ * Guarantees that the LOAD operations generated before the barrier\n+ * occur before the LOAD operations generated after.\n+ */\n+#define\trte_rmb() {asm volatile(\"dsb ld\" : : : \"memory\"); }\n+\n+\n+\n+/*------------------------- 16 bit atomic operations -------------------------*/\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+static inline int\n+rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline void\n+rte_atomic16_inc(rte_atomic16_t *v)\n+{\n+\trte_atomic16_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic16_dec(rte_atomic16_t *v)\n+{\n+\trte_atomic16_sub(v, 1);\n+}\n+\n+static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)\n+{\n+\treturn (__sync_add_and_fetch(&v->cnt, 1) == 0);\n+}\n+\n+static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)\n+{\n+\treturn (__sync_sub_and_fetch(&v->cnt, 1) == 0);\n+}\n+\n+static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)\n+{\n+\treturn rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);\n+}\n+\n+\n+/*------------------------- 32 bit atomic operations -------------------------*/\n+\n+static inline int\n+rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline void\n+rte_atomic32_inc(rte_atomic32_t *v)\n+{\n+\trte_atomic32_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic32_dec(rte_atomic32_t *v)\n+{\n+\trte_atomic32_sub(v, 1);\n+}\n+\n+static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)\n+{\n+\treturn (__sync_add_and_fetch(&v->cnt, 1) == 0);\n+}\n+\n+static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)\n+{\n+\treturn (__sync_sub_and_fetch(&v->cnt, 1) == 0);\n+}\n+\n+static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)\n+{\n+\treturn rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);\n+}\n+\n+/*------------------------- 64 bit atomic operations -------------------------*/\n+\n+static inline int\n+rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)\n+{\n+\treturn __sync_bool_compare_and_swap(dst, exp, src);\n+}\n+\n+static inline void\n+rte_atomic64_init(rte_atomic64_t *v)\n+{\n+#ifdef __LP64__\n+\tv->cnt = 0;\n+#else\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n+\t\t\t\t\ttmp, 0);\n+\t}\n+#endif\n+}\n+\n+static inline int64_t\n+rte_atomic64_read(rte_atomic64_t *v)\n+{\n+#ifdef __LP64__\n+\treturn v->cnt;\n+#else\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\t/* replace the value by itself */\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n+\t\t\t\t\ttmp, tmp);\n+\t}\n+\treturn tmp;\n+#endif\n+}\n+\n+static inline void\n+rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)\n+{\n+#ifdef __LP64__\n+\tv->cnt = new_value;\n+#else\n+\tint success = 0;\n+\tuint64_t tmp;\n+\n+\twhile (success == 0) {\n+\t\ttmp = v->cnt;\n+\t\tsuccess = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,\n+\t\t\t\t\ttmp, new_value);\n+\t}\n+#endif\n+}\n+\n+static inline void\n+rte_atomic64_add(rte_atomic64_t *v, int64_t inc)\n+{\n+\t__sync_fetch_and_add(&v->cnt, inc);\n+}\n+\n+static inline void\n+rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)\n+{\n+\t__sync_fetch_and_sub(&v->cnt, dec);\n+}\n+\n+static inline void\n+rte_atomic64_inc(rte_atomic64_t *v)\n+{\n+\trte_atomic64_add(v, 1);\n+}\n+\n+static inline void\n+rte_atomic64_dec(rte_atomic64_t *v)\n+{\n+\trte_atomic64_sub(v, 1);\n+}\n+\n+static inline int64_t\n+rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)\n+{\n+\treturn __sync_add_and_fetch(&v->cnt, inc);\n+}\n+\n+static inline int64_t\n+rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)\n+{\n+\treturn __sync_sub_and_fetch(&v->cnt, dec);\n+}\n+\n+static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_add_return(v, 1) == 0;\n+}\n+\n+static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_sub_return(v, 1) == 0;\n+}\n+\n+static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)\n+{\n+\treturn rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);\n+}\n+\n+static inline void rte_atomic64_clear(rte_atomic64_t *v)\n+{\n+\trte_atomic64_set(v, 0);\n+}\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ATOMIC_ARM64_H_ */\n",
    "prefixes": [
        "dpdk-dev",
        "01/11"
    ]
}