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put:
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GET /api/patches/79348/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 79348,
    "url": "http://patches.dpdk.org/api/patches/79348/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200930130415.11211-12-ciara.power@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200930130415.11211-12-ciara.power@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200930130415.11211-12-ciara.power@intel.com",
    "date": "2020-09-30T13:04:07",
    "name": "[v3,11/18] net/ixgbe: add checks for max SIMD bitwidth",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "dda999230076b6d94425118b534f52fc2b1f41ec",
    "submitter": {
        "id": 978,
        "url": "http://patches.dpdk.org/api/people/978/?format=api",
        "name": "Power, Ciara",
        "email": "ciara.power@intel.com"
    },
    "delegate": {
        "id": 24651,
        "url": "http://patches.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200930130415.11211-12-ciara.power@intel.com/mbox/",
    "series": [
        {
            "id": 12621,
            "url": "http://patches.dpdk.org/api/series/12621/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12621",
            "date": "2020-09-30T13:03:56",
            "name": "add max SIMD bitwidth to EAL",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/12621/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/79348/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/79348/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 64F98A04B5;\n\tWed, 30 Sep 2020 15:11:48 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D21651DB71;\n\tWed, 30 Sep 2020 15:08:33 +0200 (CEST)",
            "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id D7E851DB2B\n for <dev@dpdk.org>; Wed, 30 Sep 2020 15:08:20 +0200 (CEST)",
            "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Sep 2020 06:08:19 -0700",
            "from silpixa00399953.ir.intel.com (HELO\n silpixa00399953.ger.corp.intel.com) ([10.237.222.53])\n by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:18 -0700"
        ],
        "IronPort-SDR": [
            "\n eKPv//LyTdqjumNka2cW+Py4HrDtnBLCUve8QvxNA/N2aVO3T9SYYKqpwcoclrQQWuzCNlCgML\n FmeYT8Fn7QxA==",
            "\n Zl3qk6+2MfscKreBI+8qorgvDf9xz2lXnqgk67fVVVj5vldNmRzCoDJz8mRKNJxg3d4dJ3Y724\n H9+vMQ77rZpQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9759\"; a=\"150223485\"",
            "E=Sophos;i=\"5.77,322,1596524400\"; d=\"scan'208\";a=\"150223485\"",
            "E=Sophos;i=\"5.77,322,1596524400\"; d=\"scan'208\";a=\"294603239\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Ciara Power <ciara.power@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Ciara Power <ciara.power@intel.com>, Wei Zhao <wei.zhao1@intel.com>,\n Jeff Guo <jia.guo@intel.com>, Haiyue Wang <haiyue.wang@intel.com>",
        "Date": "Wed, 30 Sep 2020 14:04:07 +0100",
        "Message-Id": "<20200930130415.11211-12-ciara.power@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20200930130415.11211-1-ciara.power@intel.com>",
        "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20200930130415.11211-1-ciara.power@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 11/18] net/ixgbe: add checks for max SIMD\n\tbitwidth",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "When choosing a vector path to take, an extra condition must be\nsatisfied to ensure the max SIMD bitwidth allows for the CPU enabled\npath.\n\nCc: Wei Zhao <wei.zhao1@intel.com>\nCc: Jeff Guo <jia.guo@intel.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n---\n drivers/net/ixgbe/ixgbe_rxtx.c | 7 +++++--\n 1 file changed, 5 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex 977ecf5137..eadc7183f2 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -2503,7 +2503,9 @@ ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)\n \t\tdev->tx_pkt_prepare = NULL;\n \t\tif (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&\n \t\t\t\t(rte_eal_process_type() != RTE_PROC_PRIMARY ||\n-\t\t\t\t\tixgbe_txq_vec_setup(txq) == 0)) {\n+\t\t\t\t\tixgbe_txq_vec_setup(txq) == 0) &&\n+\t\t\t\trte_get_max_simd_bitwidth()\n+\t\t\t\t>= RTE_MAX_128_SIMD) {\n \t\t\tPMD_INIT_LOG(DEBUG, \"Vector tx enabled.\");\n \t\t\tdev->tx_pkt_burst = ixgbe_xmit_pkts_vec;\n \t\t} else\n@@ -4743,7 +4745,8 @@ ixgbe_set_rx_function(struct rte_eth_dev *dev)\n \t * conditions to be met and Rx Bulk Allocation should be allowed.\n \t */\n \tif (ixgbe_rx_vec_dev_conf_condition_check(dev) ||\n-\t    !adapter->rx_bulk_alloc_allowed) {\n+\t    !adapter->rx_bulk_alloc_allowed ||\n+\t\t\trte_get_max_simd_bitwidth() < RTE_MAX_128_SIMD) {\n \t\tPMD_INIT_LOG(DEBUG, \"Port[%d] doesn't meet Vector Rx \"\n \t\t\t\t    \"preconditions\",\n \t\t\t     dev->data->port_id);\n",
    "prefixes": [
        "v3",
        "11/18"
    ]
}