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GET /api/patches/78578/?format=api
{ "id": 78578, "url": "http://patches.dpdk.org/api/patches/78578/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200923142253.18853-4-radu.nicolau@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200923142253.18853-4-radu.nicolau@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200923142253.18853-4-radu.nicolau@intel.com", "date": "2020-09-23T14:22:51", "name": "[v12,3/5] common/qat: use WC store to update queue tail registers", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7492cbe0cb2cc4f5ff9159b8e511ba91a8a55c63", "submitter": { "id": 743, "url": "http://patches.dpdk.org/api/people/743/?format=api", "name": "Radu Nicolau", "email": "radu.nicolau@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200923142253.18853-4-radu.nicolau@intel.com/mbox/", "series": [ { "id": 12444, "url": "http://patches.dpdk.org/api/series/12444/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12444", "date": "2020-09-23T14:22:48", "name": "eal: add WC store functions", "version": 12, "mbox": "http://patches.dpdk.org/series/12444/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/78578/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/78578/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2678EA04B1;\n\tWed, 23 Sep 2020 16:24:10 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BFB841DB92;\n\tWed, 23 Sep 2020 16:23:50 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by dpdk.org (Postfix) with ESMTP id D39861DCA5\n for <dev@dpdk.org>; Wed, 23 Sep 2020 16:23:47 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 Sep 2020 07:23:47 -0700", "from silpixa00399477.ir.intel.com ([10.237.214.232])\n by fmsmga005.fm.intel.com with ESMTP; 23 Sep 2020 07:23:44 -0700" ], "IronPort-SDR": [ "\n 5JgJLfDqj6/wGZDM8WRzZozsftuwV/Z9Sg0bIlciSHz3NjPa9Uu0fUcFkfSVSDjX++Mqrk2p0M\n Tj+nuwPREsgQ==", "\n cU2dUqksQe19ROxXUBxB0iCW4r2aoOLlWH4+kBm8U3gOV8FKWePbAPg+UgZ7+wSVAowOkjqWIL\n qkPumpaiEP0w==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9752\"; a=\"245732155\"", "E=Sophos;i=\"5.77,293,1596524400\"; d=\"scan'208\";a=\"245732155\"", "E=Sophos;i=\"5.77,293,1596524400\"; d=\"scan'208\";a=\"511663518\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Radu Nicolau <radu.nicolau@intel.com>", "To": "dev@dpdk.org", "Cc": "beilei.xing@intel.com, jia.guo@intel.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, jerinjacobk@gmail.com,\n david.marchand@redhat.com, fiona.trahe@intel.com, wei.zhao1@intel.com,\n ruifeng.wang@arm.com, qiming.yang@intel.com, qi.z.zhang@intel.com,\n Radu Nicolau <radu.nicolau@intel.com>", "Date": "Wed, 23 Sep 2020 14:22:51 +0000", "Message-Id": "<20200923142253.18853-4-radu.nicolau@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200923142253.18853-1-radu.nicolau@intel.com>", "References": "<1591870283-7776-1-git-send-email-radu.nicolau@intel.com>\n <20200923142253.18853-1-radu.nicolau@intel.com>", "Subject": "[dpdk-dev] [PATCH v12 3/5] common/qat: use WC store to update queue\n\ttail registers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Performance improvement: use a write combining store\ninstead of a regular mmio write to update queue tail\nregisters.\n\nSigned-off-by: Radu Nicolau <radu.nicolau@intel.com>\nAcked-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n doc/guides/rel_notes/release_20_11.rst | 4 ++++\n drivers/common/qat/qat_adf/adf_transport_access_macros.h | 6 ++++--\n 2 files changed, 8 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex c0307893e..3d310572c 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -89,6 +89,10 @@ New Features\n \n Updated the Intel i40e driver to use write combining stores.\n \n+* **Updated Intel qat driver.**\n+\n+ Updated the Intel qat driver to use write combining stores.\n+\n Removed Items\n -------------\n \ndiff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h\nindex 1eef5513f..504ffb723 100644\n--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h\n+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h\n@@ -9,6 +9,8 @@\n /* CSR write macro */\n #define ADF_CSR_WR(csrAddr, csrOffset, val)\t\t\\\n \trte_write32(val, (((uint8_t *)csrAddr) + csrOffset))\n+#define ADF_CSR_WC_WR(csrAddr, csrOffset, val)\t\t\\\n+\trte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset))\n \n /* CSR read macro */\n #define ADF_CSR_RD(csrAddr, csrOffset)\t\t\t\\\n@@ -110,10 +112,10 @@ do { \\\n \t\tADF_RING_CSR_RING_UBASE + (ring << 2), u_base);\t\\\n } while (0)\n #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \\\n-\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\tADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n \t\tADF_RING_CSR_RING_HEAD + (ring << 2), value)\n #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \\\n-\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\tADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n \t\tADF_RING_CSR_RING_TAIL + (ring << 2), value)\n #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \\\n do { \\\n", "prefixes": [ "v12", "3/5" ] }