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GET /api/patches/77418/?format=api
http://patches.dpdk.org/api/patches/77418/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-32-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200911131954.15999-32-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200911131954.15999-32-qi.z.zhang@intel.com", "date": "2020-09-11T13:19:45", "name": "[v2,31/40] net/ice/base: adjust rate limit profile ids runtime database", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "fe795dfc9d605a5cb54f7554fe3bc1f04fa31774", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200911131954.15999-32-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 12148, "url": "http://patches.dpdk.org/api/series/12148/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12148", "date": "2020-09-11T13:19:15", "name": "ice base code update", "version": 2, "mbox": "http://patches.dpdk.org/series/12148/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/77418/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/77418/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 534B7A04B7;\n\tFri, 11 Sep 2020 15:22:22 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EB0E21C235;\n\tFri, 11 Sep 2020 15:16:59 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id 978211C210\n for <dev@dpdk.org>; Fri, 11 Sep 2020 15:16:46 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Sep 2020 06:16:45 -0700", "from dpdk51.sh.intel.com ([10.67.111.82])\n by FMSMGA003.fm.intel.com with ESMTP; 11 Sep 2020 06:16:44 -0700" ], "IronPort-SDR": [ "\n 1eGFjVZxNxi6sH4nBtQIMJuCy8qSUMTCYflGia83M0nYUpVdl/d7yKfhVrJZcpU2UaigvM7V8j\n nVmdfJxl8tCg==", "\n ahJ8cZPQlwVExJf0RMCdCtg1fdl6n3Z82ix5x1AObr7IDj8FEJpiJUS/z8tbOHCDHAz8LXQ6fz\n IBuZ9BhgH8Rg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9740\"; a=\"146482385\"", "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"146482385\"", "E=Sophos;i=\"5.76,415,1592895600\"; d=\"scan'208\";a=\"342296729\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "ferruh.yigit@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Shibin Koikkara Reeny <shibin.koikkara.reeny@intel.com>", "Date": "Fri, 11 Sep 2020 21:19:45 +0800", "Message-Id": "<20200911131954.15999-32-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200911131954.15999-1-qi.z.zhang@intel.com>", "References": "<20200907112826.48493-1-qi.z.zhang@intel.com>\n <20200911131954.15999-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 31/40] net/ice/base: adjust rate limit profile\n\tids runtime database", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Moving the runtime profile ids database/storage to the hw structure.\n\nSigned-off-by: Shibin Koikkara Reeny <shibin.koikkara.reeny@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_sched.c | 54 +++++++++++++++++++---------------------\n drivers/net/ice/base/ice_type.h | 4 +--\n 2 files changed, 28 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex 1374b9a09..4be449f61 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -727,15 +727,15 @@ ice_sched_del_rl_profile(struct ice_hw *hw,\n static void ice_sched_clear_rl_prof(struct ice_port_info *pi)\n {\n \tu16 ln;\n+\tstruct ice_hw *hw = pi->hw;\n \n-\tfor (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {\n+\tfor (ln = 0; ln < hw->num_tx_sched_layers; ln++) {\n \t\tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n \t\tstruct ice_aqc_rl_profile_info *rl_prof_tmp;\n \n \t\tLIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp,\n-\t\t\t\t\t &pi->rl_prof_list[ln],\n+\t\t\t\t\t &hw->rl_prof_list[ln],\n \t\t\t\t\t ice_aqc_rl_profile_info, list_entry) {\n-\t\t\tstruct ice_hw *hw = pi->hw;\n \t\t\tenum ice_status status;\n \n \t\t\trl_prof_elem->prof_id_ref = 0;\n@@ -1260,7 +1260,7 @@ enum ice_status ice_sched_init_port(struct ice_port_info *pi)\n \tpi->port_state = ICE_SCHED_PORT_STATE_READY;\n \tice_init_lock(&pi->sched_lock);\n \tfor (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++)\n-\t\tINIT_LIST_HEAD(&pi->rl_prof_list[i]);\n+\t\tINIT_LIST_HEAD(&hw->rl_prof_list[i]);\n \n err_init_port:\n \tif (status && pi->root) {\n@@ -2868,24 +2868,24 @@ ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id,\n \n /**\n * ice_sched_rm_unused_rl_prof - remove unused RL profile\n- * @pi: port information structure\n+ * @hw: pointer to the hardware structure\n *\n * This function removes unused rate limit profiles from the HW and\n * SW DB. The caller needs to hold scheduler lock.\n */\n-static void ice_sched_rm_unused_rl_prof(struct ice_port_info *pi)\n+static void ice_sched_rm_unused_rl_prof(struct ice_hw *hw)\n {\n \tu16 ln;\n \n-\tfor (ln = 0; ln < pi->hw->num_tx_sched_layers; ln++) {\n+\tfor (ln = 0; ln < hw->num_tx_sched_layers; ln++) {\n \t\tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n \t\tstruct ice_aqc_rl_profile_info *rl_prof_tmp;\n \n \t\tLIST_FOR_EACH_ENTRY_SAFE(rl_prof_elem, rl_prof_tmp,\n-\t\t\t\t\t &pi->rl_prof_list[ln],\n+\t\t\t\t\t &hw->rl_prof_list[ln],\n \t\t\t\t\t ice_aqc_rl_profile_info, list_entry) {\n-\t\t\tif (!ice_sched_del_rl_profile(pi->hw, rl_prof_elem))\n-\t\t\t\tice_debug(pi->hw, ICE_DBG_SCHED, \"Removed rl profile\\n\");\n+\t\t\tif (!ice_sched_del_rl_profile(hw, rl_prof_elem))\n+\t\t\t\tice_debug(hw, ICE_DBG_SCHED, \"Removed rl profile\\n\");\n \t\t}\n \t}\n }\n@@ -3031,7 +3031,7 @@ enum ice_status ice_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id)\n \tice_free(pi->hw, agg_info);\n \n \t/* Remove unused RL profile IDs from HW and SW DB */\n-\tice_sched_rm_unused_rl_prof(pi);\n+\tice_sched_rm_unused_rl_prof(pi->hw);\n \n exit_ice_rm_agg_cfg:\n \tice_release_lock(&pi->sched_lock);\n@@ -3852,7 +3852,7 @@ ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw,\n \n /**\n * ice_sched_add_rl_profile - add RL profile\n- * @pi: port information structure\n+ * @hw: pointer to the hardware structure\n * @rl_type: type of rate limit BW - min, max, or shared\n * @bw: bandwidth in Kbps - Kilo bits per sec\n * @layer_num: specifies in which layer to create profile\n@@ -3864,14 +3864,13 @@ ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw,\n * The caller needs to hold the scheduler lock.\n */\n static struct ice_aqc_rl_profile_info *\n-ice_sched_add_rl_profile(struct ice_port_info *pi,\n-\t\t\t enum ice_rl_type rl_type, u32 bw, u8 layer_num)\n+ice_sched_add_rl_profile(struct ice_hw *hw, enum ice_rl_type rl_type,\n+\t\t\t u32 bw, u8 layer_num)\n {\n \tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n \tu16 profiles_added = 0, num_profiles = 1;\n \tstruct ice_aqc_rl_profile_elem *buf;\n \tenum ice_status status;\n-\tstruct ice_hw *hw;\n \tu8 profile_type;\n \n \tif (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)\n@@ -3890,10 +3889,9 @@ ice_sched_add_rl_profile(struct ice_port_info *pi,\n \t\treturn NULL;\n \t}\n \n-\tif (!pi)\n+\tif (!hw)\n \t\treturn NULL;\n-\thw = pi->hw;\n-\tLIST_FOR_EACH_ENTRY(rl_prof_elem, &pi->rl_prof_list[layer_num],\n+\tLIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num],\n \t\t\t ice_aqc_rl_profile_info, list_entry)\n \t\tif ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) ==\n \t\t profile_type && rl_prof_elem->bw == bw)\n@@ -3926,7 +3924,7 @@ ice_sched_add_rl_profile(struct ice_port_info *pi,\n \n \t/* Good entry - add in the list */\n \trl_prof_elem->prof_id_ref = 0;\n-\tLIST_ADD(&rl_prof_elem->list_entry, &pi->rl_prof_list[layer_num]);\n+\tLIST_ADD(&rl_prof_elem->list_entry, &hw->rl_prof_list[layer_num]);\n \treturn rl_prof_elem;\n \n exit_add_rl_prof:\n@@ -4105,7 +4103,7 @@ ice_sched_get_srl_node(struct ice_sched_node *node, u8 srl_layer)\n \n /**\n * ice_sched_rm_rl_profile - remove RL profile ID\n- * @pi: port information structure\n+ * @hw: pointer to the hardware structure\n * @layer_num: layer number where profiles are saved\n * @profile_type: profile type like EIR, CIR, or SRL\n * @profile_id: profile ID to remove\n@@ -4115,7 +4113,7 @@ ice_sched_get_srl_node(struct ice_sched_node *node, u8 srl_layer)\n * scheduler lock.\n */\n static enum ice_status\n-ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type,\n+ice_sched_rm_rl_profile(struct ice_hw *hw, u8 layer_num, u8 profile_type,\n \t\t\tu16 profile_id)\n {\n \tstruct ice_aqc_rl_profile_info *rl_prof_elem;\n@@ -4124,7 +4122,7 @@ ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type,\n \tif (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)\n \t\treturn ICE_ERR_PARAM;\n \t/* Check the existing list for RL profile */\n-\tLIST_FOR_EACH_ENTRY(rl_prof_elem, &pi->rl_prof_list[layer_num],\n+\tLIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num],\n \t\t\t ice_aqc_rl_profile_info, list_entry)\n \t\tif ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) ==\n \t\t profile_type &&\n@@ -4134,9 +4132,9 @@ ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type,\n \t\t\t\trl_prof_elem->prof_id_ref--;\n \n \t\t\t/* Remove old profile ID from database */\n-\t\t\tstatus = ice_sched_del_rl_profile(pi->hw, rl_prof_elem);\n+\t\t\tstatus = ice_sched_del_rl_profile(hw, rl_prof_elem);\n \t\t\tif (status && status != ICE_ERR_IN_USE)\n-\t\t\t\tice_debug(pi->hw, ICE_DBG_SCHED, \"Remove rl profile failed\\n\");\n+\t\t\t\tice_debug(hw, ICE_DBG_SCHED, \"Remove rl profile failed\\n\");\n \t\t\tbreak;\n \t\t}\n \tif (status == ICE_ERR_IN_USE)\n@@ -4196,7 +4194,7 @@ ice_sched_set_node_bw_dflt(struct ice_port_info *pi,\n \t old_id == ICE_SCHED_INVAL_PROF_ID)\n \t\treturn ICE_SUCCESS;\n \n-\treturn ice_sched_rm_rl_profile(pi, layer_num, profile_type, old_id);\n+\treturn ice_sched_rm_rl_profile(hw, layer_num, profile_type, old_id);\n }\n \n /**\n@@ -4265,7 +4263,7 @@ ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,\n \tstruct ice_hw *hw = pi->hw;\n \tu16 old_id, rl_prof_id;\n \n-\trl_prof_info = ice_sched_add_rl_profile(pi, rl_type, bw, layer_num);\n+\trl_prof_info = ice_sched_add_rl_profile(hw, rl_type, bw, layer_num);\n \tif (!rl_prof_info)\n \t\treturn status;\n \n@@ -4287,7 +4285,7 @@ ice_sched_set_node_bw(struct ice_port_info *pi, struct ice_sched_node *node,\n \t old_id == ICE_SCHED_INVAL_PROF_ID || old_id == rl_prof_id)\n \t\treturn ICE_SUCCESS;\n \n-\treturn ice_sched_rm_rl_profile(pi, layer_num,\n+\treturn ice_sched_rm_rl_profile(hw, layer_num,\n \t\t\t\t rl_prof_info->profile.flags &\n \t\t\t\t ICE_AQC_RL_PROFILE_TYPE_M, old_id);\n }\n@@ -4316,7 +4314,7 @@ ice_sched_set_node_bw_lmt(struct ice_port_info *pi, struct ice_sched_node *node,\n \t\treturn ICE_ERR_PARAM;\n \thw = pi->hw;\n \t/* Remove unused RL profile IDs from HW and SW DB */\n-\tice_sched_rm_unused_rl_prof(pi);\n+\tice_sched_rm_unused_rl_prof(hw);\n \tlayer_num = ice_sched_get_rl_prof_layer(pi, rl_type,\n \t\t\t\t\t\tnode->tx_sched_layer);\n \tif (layer_num >= hw->num_tx_sched_layers)\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex f80e19df9..9c2fb560e 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -782,8 +782,6 @@ struct ice_port_info {\n \tstruct ice_lock sched_lock;\t/* protect access to TXSched tree */\n \tstruct ice_sched_node *\n \t\tsib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];\n-\t/* List contain profile ID(s) and other params per layer */\n-\tstruct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n \tstruct ice_bw_type_info root_node_bw_t_info;\n \tstruct ice_bw_type_info tc_node_bw_t_info[ICE_MAX_TRAFFIC_CLASS];\n \tstruct ice_qos_cfg qos_cfg;\n@@ -834,6 +832,8 @@ struct ice_hw {\n \tu8 sw_entry_point_layer;\n \tu16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n \tstruct LIST_HEAD_TYPE agg_list;\t/* lists all aggregator */\n+\t/* List contain profile ID(s) and other params per layer */\n+\tstruct LIST_HEAD_TYPE rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n \tstruct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];\n \tu8 evb_veb;\t\t/* true for VEB, false for VEPA */\n \tu8 reset_ongoing;\t/* true if HW is in reset, false otherwise */\n", "prefixes": [ "v2", "31/40" ] }{ "id": 77418, "url": "