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GET /api/patches/77212/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 77212,
    "url": "http://patches.dpdk.org/api/patches/77212/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1599763717-135002-3-git-send-email-savinay.dharmappa@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1599763717-135002-3-git-send-email-savinay.dharmappa@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1599763717-135002-3-git-send-email-savinay.dharmappa@intel.com",
    "date": "2020-09-10T18:48:29",
    "name": "[v2,02/10] sched: add subport profile table",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "d9e22c24cff7c98580756f34314c10c6197677c8",
    "submitter": {
        "id": 1535,
        "url": "http://patches.dpdk.org/api/people/1535/?format=api",
        "name": "Savinay Dharmappa",
        "email": "savinay.dharmappa@intel.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1599763717-135002-3-git-send-email-savinay.dharmappa@intel.com/mbox/",
    "series": [
        {
            "id": 12110,
            "url": "http://patches.dpdk.org/api/series/12110/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12110",
            "date": "2020-09-10T18:48:27",
            "name": "Enable dynamic config of subport bandwidth",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/12110/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/77212/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/77212/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7D803A04B5;\n\tThu, 10 Sep 2020 20:49:18 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BD9FC1C0D9;\n\tThu, 10 Sep 2020 20:48:55 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id DE0011BFB4\n for <dev@dpdk.org>; Thu, 10 Sep 2020 20:48:49 +0200 (CEST)",
            "from orsmga007.jf.intel.com ([10.7.209.58])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 10 Sep 2020 11:48:47 -0700",
            "from silpixa00400629.ir.intel.com ([10.237.214.135])\n by orsmga007.jf.intel.com with ESMTP; 10 Sep 2020 11:48:46 -0700"
        ],
        "IronPort-SDR": [
            "\n gYg9ljvrkq8zQDASly4yk5FCJakICcnXlNLxfmCO1ocNB63jRkCZ80IDEAI8CnEzqrDA0uZNt2\n S+LRmlGDn3WA==",
            "\n yL0V6ial2Ot7sRQXGQgPyYcBbyNwcmwH5qnNNULO3+fR38t+v8qdXSmuVEa9VPVHt4LL/JjE7C\n LYug/8JECwsA=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9740\"; a=\"138130648\"",
            "E=Sophos;i=\"5.76,413,1592895600\"; d=\"scan'208\";a=\"138130648\"",
            "E=Sophos;i=\"5.76,413,1592895600\"; d=\"scan'208\";a=\"344371074\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Savinay Dharmappa <savinay.dharmappa@intel.com>",
        "To": "jasvinder.singh@intel.com,\n\tcristian.dumitrescu@intel.com,\n\tdev@dpdk.org",
        "Cc": "savinay.dharmappa@intel.com",
        "Date": "Thu, 10 Sep 2020 19:48:29 +0100",
        "Message-Id": "<1599763717-135002-3-git-send-email-savinay.dharmappa@intel.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1599763717-135002-1-git-send-email-savinay.dharmappa@intel.com>",
        "References": "<1599037006-3931-1-git-send-email-savinay.dharmappa@intel.com>\n <1599763717-135002-1-git-send-email-savinay.dharmappa@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v2 02/10] sched: add subport profile table",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add subport profile table to internal port data structure and\nupdate the port config function.\n\nSigned-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\n---\n lib/librte_sched/rte_sched.c | 185 ++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 182 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex 474422b..ec6e6bf 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -223,6 +223,8 @@ struct rte_sched_port {\n \tuint16_t pipe_queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \tuint8_t pipe_tc[RTE_SCHED_QUEUES_PER_PIPE];\n \tuint8_t tc_queue[RTE_SCHED_QUEUES_PER_PIPE];\n+\tuint32_t n_subport_profiles;\n+\tuint32_t n_max_subport_profiles;\n \tuint64_t rate;\n \tuint32_t mtu;\n \tuint32_t frame_overhead;\n@@ -241,6 +243,7 @@ struct rte_sched_port {\n \tuint32_t subport_id;\n \n \t/* Large data structures */\n+\tstruct rte_sched_subport_profile *subport_profiles;\n \tstruct rte_sched_subport *subports[0] __rte_cache_aligned;\n } __rte_cache_aligned;\n \n@@ -387,8 +390,60 @@ pipe_profile_check(struct rte_sched_pipe_params *params,\n }\n \n static int\n+subport_profile_check(struct rte_sched_subport_profile_params *params,\n+\tuint64_t rate)\n+{\n+\tuint32_t i;\n+\n+\t/* Check user parameters */\n+\tif (params == NULL) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect value for parameter params\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tb_rate == 0 || params->tb_rate > rate) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect value for tb rate\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tb_size == 0) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect value for tb size\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\tuint64_t tc_rate = params->tc_rate[i];\n+\n+\t\tif (tc_rate == 0 || (tc_rate > params->tb_rate)) {\n+\t\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\t\"Incorrect value for tc rate\\n\", __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE] == 0) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect tc rate(best effort)\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tc_period == 0) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: \"\n+\t\t\"Incorrect value for tc period\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n rte_sched_port_check_params(struct rte_sched_port_params *params)\n {\n+\tuint32_t i;\n+\n \tif (params == NULL) {\n \t\tRTE_LOG(ERR, SCHED,\n \t\t\t\"%s: Incorrect value for parameter params\\n\", __func__);\n@@ -425,6 +480,29 @@ rte_sched_port_check_params(struct rte_sched_port_params *params)\n \t\treturn -EINVAL;\n \t}\n \n+\tif (params->subport_profiles == NULL ||\n+\t\tparams->n_subport_profiles == 0 ||\n+\t\tparams->n_max_subport_profiles == 0 ||\n+\t\tparams->n_subport_profiles > params->n_max_subport_profiles) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\"%s: Incorrect value for subport profiles\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < params->n_subport_profiles; i++) {\n+\t\tstruct rte_sched_subport_profile_params *p =\n+\t\t\t\t\t\tparams->subport_profiles + i;\n+\t\tint status;\n+\n+\t\tstatus = subport_profile_check(p, params->rate);\n+\t\tif (status != 0) {\n+\t\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: subport profile check failed(%d)\\n\",\n+\t\t\t__func__, status);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n \t/* n_pipes_per_subport: non-zero, power of 2 */\n \tif (params->n_pipes_per_subport == 0 ||\n \t    !rte_is_power_of_2(params->n_pipes_per_subport)) {\n@@ -566,6 +644,42 @@ rte_sched_port_log_pipe_profile(struct rte_sched_subport *subport, uint32_t i)\n \t\tp->wrr_cost[0], p->wrr_cost[1], p->wrr_cost[2], p->wrr_cost[3]);\n }\n \n+static void\n+rte_sched_port_log_subport_profile(struct rte_sched_port *port, uint32_t i)\n+{\n+\tstruct rte_sched_subport_profile *p = port->subport_profiles + i;\n+\n+\tRTE_LOG(DEBUG, SCHED, \"Low level config for subport profile %u:\\n\"\n+\t\"Token bucket: period = %\"PRIu64\", credits per period = %\"PRIu64\",\"\n+\t\"size = %\"PRIu64\"\\n\"\n+\t\"Traffic classes: period = %\"PRIu64\",\\n\"\n+\t\"credits per period = [%\"PRIu64\", %\"PRIu64\", %\"PRIu64\", %\"PRIu64\n+\t\" %\"PRIu64\", %\"PRIu64\", %\"PRIu64\", %\"PRIu64\", %\"PRIu64\", %\"PRIu64\n+\t\" %\"PRIu64\", %\"PRIu64\", %\"PRIu64\"]\\n\",\n+\ti,\n+\n+\t/* Token bucket */\n+\tp->tb_period,\n+\tp->tb_credits_per_period,\n+\tp->tb_size,\n+\n+\t/* Traffic classes */\n+\tp->tc_period,\n+\tp->tc_credits_per_period[0],\n+\tp->tc_credits_per_period[1],\n+\tp->tc_credits_per_period[2],\n+\tp->tc_credits_per_period[3],\n+\tp->tc_credits_per_period[4],\n+\tp->tc_credits_per_period[5],\n+\tp->tc_credits_per_period[6],\n+\tp->tc_credits_per_period[7],\n+\tp->tc_credits_per_period[8],\n+\tp->tc_credits_per_period[9],\n+\tp->tc_credits_per_period[10],\n+\tp->tc_credits_per_period[11],\n+\tp->tc_credits_per_period[12]);\n+}\n+\n static inline uint64_t\n rte_sched_time_ms_to_bytes(uint64_t time_ms, uint64_t rate)\n {\n@@ -635,6 +749,37 @@ rte_sched_pipe_profile_convert(struct rte_sched_subport *subport,\n }\n \n static void\n+rte_sched_subport_profile_convert(struct rte_sched_subport_profile_params *src,\n+\tstruct rte_sched_subport_profile *dst,\n+\tuint64_t rate)\n+{\n+\tuint32_t i;\n+\n+\t/* Token Bucket */\n+\tif (src->tb_rate == rate) {\n+\t\tdst->tb_credits_per_period = 1;\n+\t\tdst->tb_period = 1;\n+\t} else {\n+\t\tdouble tb_rate = (double) src->tb_rate\n+\t\t\t\t/ (double) rate;\n+\t\tdouble d = RTE_SCHED_TB_RATE_CONFIG_ERR;\n+\n+\t\trte_approx_64(tb_rate, d, &dst->tb_credits_per_period,\n+\t\t\t&dst->tb_period);\n+\t}\n+\n+\tdst->tb_size = src->tb_size;\n+\n+\t/* Traffic Classes */\n+\tdst->tc_period = rte_sched_time_ms_to_bytes(src->tc_period, rate);\n+\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n+\t\tdst->tc_credits_per_period[i]\n+\t\t\t= rte_sched_time_ms_to_bytes(src->tc_period,\n+\t\t\t\tsrc->tc_rate[i]);\n+}\n+\n+static void\n rte_sched_subport_config_pipe_profile_table(struct rte_sched_subport *subport,\n \tstruct rte_sched_subport_params *params, uint64_t rate)\n {\n@@ -658,6 +803,24 @@ rte_sched_subport_config_pipe_profile_table(struct rte_sched_subport *subport,\n \t}\n }\n \n+static void\n+rte_sched_port_config_subport_profile_table(struct rte_sched_port *port,\n+\tstruct rte_sched_port_params *params,\n+\tuint64_t rate)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < port->n_subport_profiles; i++) {\n+\t\tstruct rte_sched_subport_profile_params *src\n+\t\t\t\t= params->subport_profiles + i;\n+\t\tstruct rte_sched_subport_profile *dst\n+\t\t\t\t= port->subport_profiles + i;\n+\n+\t\trte_sched_subport_profile_convert(src, dst, rate);\n+\t\trte_sched_port_log_subport_profile(port, i);\n+\t}\n+}\n+\n static int\n rte_sched_subport_check_params(struct rte_sched_subport_params *params,\n \tuint32_t n_max_pipes_per_subport,\n@@ -804,7 +967,7 @@ struct rte_sched_port *\n rte_sched_port_config(struct rte_sched_port_params *params)\n {\n \tstruct rte_sched_port *port = NULL;\n-\tuint32_t size0, size1;\n+\tuint32_t size0, size1, size2;\n \tuint32_t cycles_per_byte;\n \tuint32_t i, j;\n \tint status;\n@@ -819,10 +982,21 @@ rte_sched_port_config(struct rte_sched_port_params *params)\n \n \tsize0 = sizeof(struct rte_sched_port);\n \tsize1 = params->n_subports_per_port * sizeof(struct rte_sched_subport *);\n+\tsize2 = params->n_max_subport_profiles *\n+\t\tsizeof(struct rte_sched_subport_profile);\n \n \t/* Allocate memory to store the data structures */\n-\tport = rte_zmalloc_socket(\"qos_params\", size0 + size1, RTE_CACHE_LINE_SIZE,\n-\t\tparams->socket);\n+\tport = rte_zmalloc_socket(\"qos_params\", size0 + size1,\n+\t\t\t\t RTE_CACHE_LINE_SIZE, params->socket);\n+\tif (port == NULL) {\n+\t\tRTE_LOG(ERR, SCHED, \"%s: Memory allocation fails\\n\", __func__);\n+\n+\t\treturn NULL;\n+\t}\n+\n+\t/* Allocate memory to store the subport profile */\n+\tport->subport_profiles  = rte_zmalloc_socket(\"subport_profile\", size2,\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE, params->socket);\n \tif (port == NULL) {\n \t\tRTE_LOG(ERR, SCHED, \"%s: Memory allocation fails\\n\", __func__);\n \n@@ -831,6 +1005,8 @@ rte_sched_port_config(struct rte_sched_port_params *params)\n \n \t/* User parameters */\n \tport->n_subports_per_port = params->n_subports_per_port;\n+\tport->n_subport_profiles = params->n_subport_profiles;\n+\tport->n_max_subport_profiles = params->n_max_subport_profiles;\n \tport->n_pipes_per_subport = params->n_pipes_per_subport;\n \tport->n_pipes_per_subport_log2 =\n \t\t\t__builtin_ctz(params->n_pipes_per_subport);\n@@ -861,6 +1037,9 @@ rte_sched_port_config(struct rte_sched_port_params *params)\n \tport->time_cpu_bytes = 0;\n \tport->time = 0;\n \n+\t/* Subport profile table */\n+\trte_sched_port_config_subport_profile_table(port, params, port->rate);\n+\n \tcycles_per_byte = (rte_get_tsc_hz() << RTE_SCHED_TIME_SHIFT)\n \t\t/ params->rate;\n \tport->inv_cycles_per_byte = rte_reciprocal_value(cycles_per_byte);\n",
    "prefixes": [
        "v2",
        "02/10"
    ]
}