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GET /api/patches/76947/?format=api
{ "id": 76947, "url": "http://patches.dpdk.org/api/patches/76947/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-15-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200908201830.74206-15-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200908201830.74206-15-cristian.dumitrescu@intel.com", "date": "2020-09-08T20:18:03", "name": "[v3,14/41] pipeline: introduce SWX add instruction", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "28c59856d1fb6a8f88847c185d3c1c596e02ca0b", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-15-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 12034, "url": "http://patches.dpdk.org/api/series/12034/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12034", "date": "2020-09-08T20:17:52", "name": "Pipeline alignment with the P4 language", "version": 3, "mbox": "http://patches.dpdk.org/series/12034/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76947/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76947/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 684DEA04B1;\n\tTue, 8 Sep 2020 22:21:19 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5B8631C1AE;\n\tTue, 8 Sep 2020 22:19:20 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id 550291C10E\n for <dev@dpdk.org>; Tue, 8 Sep 2020 22:19:00 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Sep 2020 13:18:46 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:18:45 -0700" ], "IronPort-SDR": [ "\n k7oH2nGBmJwIS65cAiJvZjqAcag2IHFmdlUCSeFWvZkSDiXmT094WgPRWm7Wq26qNaTTkqQ0SR\n MoYg7z0mC8HQ==", "\n 1d32x20Ye+61eVW6h+c0ST7vDvXmi0kj7v6U1GTCIT8UAqhZotiSU9W56KJqn4Aa0YHP6ReIQD\n pvqoBjPougoQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9738\"; a=\"145939404\"", "E=Sophos;i=\"5.76,407,1592895600\"; d=\"scan'208\";a=\"145939404\"", "E=Sophos;i=\"5.76,406,1592895600\"; d=\"scan'208\";a=\"504493426\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 8 Sep 2020 21:18:03 +0100", "Message-Id": "<20200908201830.74206-15-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200908201830.74206-1-cristian.dumitrescu@intel.com>", "References": "<20200907214032.95052-2-cristian.dumitrescu@intel.com>\n <20200908201830.74206-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 14/41] pipeline: introduce SWX add instruction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The add instruction source can be header field (H), meta-data field\n(M), extern object (E) or function (F) mailbox field, table entry\naction data field (T) or immediate value (I). The destination is HMEF.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/librte_pipeline/rte_swx_pipeline.c | 302 +++++++++++++++++++++++++\n 1 file changed, 302 insertions(+)", "diff": "diff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c\nindex 341afc735..6eee52f24 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.c\n+++ b/lib/librte_pipeline/rte_swx_pipeline.c\n@@ -267,6 +267,17 @@ enum instruction_type {\n \tINSTR_DMA_HT6,\n \tINSTR_DMA_HT7,\n \tINSTR_DMA_HT8,\n+\n+\t/* add dst src\n+\t * dst += src\n+\t * dst = HMEF, src = HMEFTI\n+\t */\n+\tINSTR_ALU_ADD, /* dst = MEF, src = MEF */\n+\tINSTR_ALU_ADD_MH, /* dst = MEF, src = H */\n+\tINSTR_ALU_ADD_HM, /* dst = H, src = MEF */\n+\tINSTR_ALU_ADD_HH, /* dst = H, src = H */\n+\tINSTR_ALU_ADD_MI, /* dst = MEF, src = I */\n+\tINSTR_ALU_ADD_HI, /* dst = H, src = I */\n };\n \n struct instr_operand {\n@@ -322,6 +333,7 @@ struct instruction {\n \t\tstruct instr_hdr_validity valid;\n \t\tstruct instr_dst_src mov;\n \t\tstruct instr_dma dma;\n+\t\tstruct instr_dst_src alu;\n \t};\n };\n \n@@ -436,6 +448,136 @@ struct thread {\n #define MASK64_BIT_SET(mask, pos) ((mask) | (1LLU << (pos)))\n #define MASK64_BIT_CLR(mask, pos) ((mask) & ~(1LLU << (pos)))\n \n+#define ALU(thread, ip, operator) \\\n+{ \\\n+\tuint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \\\n+\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \\\n+\tuint64_t dst64 = *dst64_ptr; \\\n+\tuint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \\\n+\tuint64_t dst = dst64 & dst64_mask; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint8_t *src_struct = (thread)->structs[(ip)->alu.src.struct_id]; \\\n+\tuint64_t *src64_ptr = (uint64_t *)&src_struct[(ip)->alu.src.offset]; \\\n+\tuint64_t src64 = *src64_ptr; \\\n+\tuint64_t src64_mask = UINT64_MAX >> (64 - (ip)->alu.src.n_bits); \\\n+\tuint64_t src = src64 & src64_mask; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t result = dst operator src; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t*dst64_ptr = (dst64 & ~dst64_mask) | (result & dst64_mask); \\\n+}\n+\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\n+#define ALU_S(thread, ip, operator) \\\n+{ \\\n+\tuint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \\\n+\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \\\n+\tuint64_t dst64 = *dst64_ptr; \\\n+\tuint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \\\n+\tuint64_t dst = dst64 & dst64_mask; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint8_t *src_struct = (thread)->structs[(ip)->alu.src.struct_id]; \\\n+\tuint64_t *src64_ptr = (uint64_t *)&src_struct[(ip)->alu.src.offset]; \\\n+\tuint64_t src64 = *src64_ptr; \\\n+\tuint64_t src = ntoh64(src64) >> (64 - (ip)->alu.src.n_bits); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t result = dst operator src; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t*dst64_ptr = (dst64 & ~dst64_mask) | (result & dst64_mask); \\\n+}\n+\n+#define ALU_MH ALU_S\n+\n+#define ALU_HM(thread, ip, operator) \\\n+{ \\\n+\tuint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \\\n+\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \\\n+\tuint64_t dst64 = *dst64_ptr; \\\n+\tuint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \\\n+\tuint64_t dst = ntoh64(dst64) >> (64 - (ip)->alu.dst.n_bits); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint8_t *src_struct = (thread)->structs[(ip)->alu.src.struct_id]; \\\n+\tuint64_t *src64_ptr = (uint64_t *)&src_struct[(ip)->alu.src.offset]; \\\n+\tuint64_t src64 = *src64_ptr; \\\n+\tuint64_t src64_mask = UINT64_MAX >> (64 - (ip)->alu.src.n_bits); \\\n+\tuint64_t src = src64 & src64_mask; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t result = dst operator src; \\\n+\tresult = hton64(result << (64 - (ip)->alu.dst.n_bits)); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t*dst64_ptr = (dst64 & ~dst64_mask) | result; \\\n+}\n+\n+#define ALU_HH(thread, ip, operator) \\\n+{ \\\n+\tuint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \\\n+\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \\\n+\tuint64_t dst64 = *dst64_ptr; \\\n+\tuint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \\\n+\tuint64_t dst = ntoh64(dst64) >> (64 - (ip)->alu.dst.n_bits); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint8_t *src_struct = (thread)->structs[(ip)->alu.src.struct_id]; \\\n+\tuint64_t *src64_ptr = (uint64_t *)&src_struct[(ip)->alu.src.offset]; \\\n+\tuint64_t src64 = *src64_ptr; \\\n+\tuint64_t src = ntoh64(src64) >> (64 - (ip)->alu.src.n_bits); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t result = dst operator src; \\\n+\tresult = hton64(result << (64 - (ip)->alu.dst.n_bits)); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t*dst64_ptr = (dst64 & ~dst64_mask) | result; \\\n+}\n+\n+#else\n+\n+#define ALU_S ALU\n+#define ALU_MH ALU\n+#define ALU_HM ALU\n+#define ALU_HH ALU\n+\n+#endif\n+\n+#define ALU_I(thread, ip, operator) \\\n+{ \\\n+\tuint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \\\n+\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \\\n+\tuint64_t dst64 = *dst64_ptr; \\\n+\tuint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \\\n+\tuint64_t dst = dst64 & dst64_mask; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t src = (ip)->alu.src_val; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t result = dst operator src; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t*dst64_ptr = (dst64 & ~dst64_mask) | (result & dst64_mask); \\\n+}\n+\n+#define ALU_MI ALU_I\n+\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\n+#define ALU_HI(thread, ip, operator) \\\n+{ \\\n+\tuint8_t *dst_struct = (thread)->structs[(ip)->alu.dst.struct_id]; \\\n+\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[(ip)->alu.dst.offset]; \\\n+\tuint64_t dst64 = *dst64_ptr; \\\n+\tuint64_t dst64_mask = UINT64_MAX >> (64 - (ip)->alu.dst.n_bits); \\\n+\tuint64_t dst = ntoh64(dst64) >> (64 - (ip)->alu.dst.n_bits); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t src = (ip)->alu.src_val; \\\n+\t\t\t\t\t\t\t\t\t \\\n+\tuint64_t result = dst operator src; \\\n+\tresult = hton64(result << (64 - (ip)->alu.dst.n_bits)); \\\n+\t\t\t\t\t\t\t\t\t \\\n+\t*dst64_ptr = (dst64 & ~dst64_mask) | result; \\\n+}\n+\n+#else\n+\n+#define ALU_HI ALU_I\n+\n+#endif\n+\n #define MOV(thread, ip) \\\n { \\\n \tuint8_t *dst_struct = (thread)->structs[(ip)->mov.dst.struct_id]; \\\n@@ -2719,6 +2861,151 @@ instr_dma_ht8_exec(struct rte_swx_pipeline *p)\n \tthread_ip_inc(p);\n }\n \n+/*\n+ * alu.\n+ */\n+static int\n+instr_alu_add_translate(struct rte_swx_pipeline *p,\n+\t\t\tstruct action *action,\n+\t\t\tchar **tokens,\n+\t\t\tint n_tokens,\n+\t\t\tstruct instruction *instr,\n+\t\t\tstruct instruction_data *data __rte_unused)\n+{\n+\tchar *dst = tokens[1], *src = tokens[2];\n+\tstruct field *fdst, *fsrc;\n+\tuint32_t dst_struct_id, src_struct_id, src_val;\n+\n+\tCHECK(n_tokens == 3, EINVAL);\n+\n+\tfdst = struct_field_parse(p, NULL, dst, &dst_struct_id);\n+\tCHECK(fdst, EINVAL);\n+\n+\t/* ADD, ADD_HM, ADD_MH, ADD_HH. */\n+\tfsrc = struct_field_parse(p, action, src, &src_struct_id);\n+\tif (fsrc) {\n+\t\tinstr->type = INSTR_ALU_ADD;\n+\t\tif (dst[0] == 'h' && src[0] == 'm')\n+\t\t\tinstr->type = INSTR_ALU_ADD_HM;\n+\t\tif (dst[0] == 'm' && src[0] == 'h')\n+\t\t\tinstr->type = INSTR_ALU_ADD_MH;\n+\t\tif (dst[0] == 'h' && src[0] == 'h')\n+\t\t\tinstr->type = INSTR_ALU_ADD_HH;\n+\n+\t\tinstr->alu.dst.struct_id = (uint8_t)dst_struct_id;\n+\t\tinstr->alu.dst.n_bits = fdst->n_bits;\n+\t\tinstr->alu.dst.offset = fdst->offset / 8;\n+\t\tinstr->alu.src.struct_id = (uint8_t)src_struct_id;\n+\t\tinstr->alu.src.n_bits = fsrc->n_bits;\n+\t\tinstr->alu.src.offset = fsrc->offset / 8;\n+\t\treturn 0;\n+\t}\n+\n+\t/* ADD_MI, ADD_HI. */\n+\tsrc_val = strtoul(src, &src, 0);\n+\tCHECK(!src[0], EINVAL);\n+\n+\tinstr->type = INSTR_ALU_ADD_MI;\n+\tif (dst[0] == 'h')\n+\t\tinstr->type = INSTR_ALU_ADD_HI;\n+\n+\tinstr->alu.dst.struct_id = (uint8_t)dst_struct_id;\n+\tinstr->alu.dst.n_bits = fdst->n_bits;\n+\tinstr->alu.dst.offset = fdst->offset / 8;\n+\tinstr->alu.src_val = (uint32_t)src_val;\n+\treturn 0;\n+}\n+\n+static inline void\n+instr_alu_add_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] add\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU(t, ip, +);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_add_mh_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] add (mh)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_MH(t, ip, +);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_add_hm_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] add (hm)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HM(t, ip, +);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_add_hh_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] add (hh)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HH(t, ip, +);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_add_mi_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] add (mi)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_MI(t, ip, +);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_alu_add_hi_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\tTRACE(\"[Thread %2u] add (hi)\\n\", p->thread_id);\n+\n+\t/* Structs. */\n+\tALU_HI(t, ip, +);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n #define RTE_SWX_INSTRUCTION_TOKENS_MAX 16\n \n static int\n@@ -2820,6 +3107,14 @@ instr_translate(struct rte_swx_pipeline *p,\n \t\t\t\t\t instr,\n \t\t\t\t\t data);\n \n+\tif (!strcmp(tokens[tpos], \"add\"))\n+\t\treturn instr_alu_add_translate(p,\n+\t\t\t\t\t action,\n+\t\t\t\t\t &tokens[tpos],\n+\t\t\t\t\t n_tokens - tpos,\n+\t\t\t\t\t instr,\n+\t\t\t\t\t data);\n+\n \tCHECK(0, EINVAL);\n }\n \n@@ -2977,6 +3272,13 @@ static instr_exec_t instruction_table[] = {\n \t[INSTR_DMA_HT6] = instr_dma_ht6_exec,\n \t[INSTR_DMA_HT7] = instr_dma_ht7_exec,\n \t[INSTR_DMA_HT8] = instr_dma_ht8_exec,\n+\n+\t[INSTR_ALU_ADD] = instr_alu_add_exec,\n+\t[INSTR_ALU_ADD_MH] = instr_alu_add_mh_exec,\n+\t[INSTR_ALU_ADD_HM] = instr_alu_add_hm_exec,\n+\t[INSTR_ALU_ADD_HH] = instr_alu_add_hh_exec,\n+\t[INSTR_ALU_ADD_MI] = instr_alu_add_mi_exec,\n+\t[INSTR_ALU_ADD_HI] = instr_alu_add_hi_exec,\n };\n \n static inline void\n", "prefixes": [ "v3", "14/41" ] }