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GET /api/patches/76933/?format=api
{ "id": 76933, "url": "http://patches.dpdk.org/api/patches/76933/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-4-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200908201830.74206-4-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200908201830.74206-4-cristian.dumitrescu@intel.com", "date": "2020-09-08T20:17:52", "name": "[v3,03/41] pipeline: add SWX pipeline output port", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8473ad75f4fd5c6ac4e2d8e7bbd50fb9cf318cba", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908201830.74206-4-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 12034, "url": "http://patches.dpdk.org/api/series/12034/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12034", "date": "2020-09-08T20:17:52", "name": "Pipeline alignment with the P4 language", "version": 3, "mbox": "http://patches.dpdk.org/series/12034/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76933/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76933/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A6730A04B1;\n\tTue, 8 Sep 2020 22:18:54 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7CB921BE85;\n\tTue, 8 Sep 2020 22:18:54 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id 545861DB8\n for <dev@dpdk.org>; Tue, 8 Sep 2020 22:18:52 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 08 Sep 2020 13:18:34 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com) ([10.237.223.107])\n by fmsmga006.fm.intel.com with ESMTP; 08 Sep 2020 13:18:33 -0700" ], "IronPort-SDR": [ "\n plPwqXUncl9czAlrOFxzI9DRgmDSZ4RD5Fvy+Z8OaPhSx4n84D0nrTeVJ0lu/D8CvZeIg14jPX\n NtAf/Qo7YuFA==", "\n jRE1NRD/WT3Gs9/MVvRRlKMZWPbmzvJGfwK2AVCKLNo6kjEh9ScKrcqte9wZq0h6DGQ3oCF+Wb\n VSuzD7FcmRKg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9738\"; a=\"145939365\"", "E=Sophos;i=\"5.76,407,1592895600\"; d=\"scan'208\";a=\"145939365\"", "E=Sophos;i=\"5.76,406,1592895600\"; d=\"scan'208\";a=\"504493361\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 8 Sep 2020 21:17:52 +0100", "Message-Id": "<20200908201830.74206-4-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200908201830.74206-1-cristian.dumitrescu@intel.com>", "References": "<20200907214032.95052-2-cristian.dumitrescu@intel.com>\n <20200908201830.74206-1-cristian.dumitrescu@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 03/41] pipeline: add SWX pipeline output port", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add output ports to the newly introduced SWX pipeline type. Each port\ninstantiates a port type that defines the port operations, e.g. ethdev\nport, PCAP port, etc. The TX interface is single packet, with packet\nbatching internally for performance.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n---\n lib/librte_pipeline/rte_pipeline_version.map | 2 +\n lib/librte_pipeline/rte_swx_pipeline.c | 200 +++++++++++++++++++\n lib/librte_pipeline/rte_swx_pipeline.h | 50 +++++\n lib/librte_port/rte_swx_port.h | 84 ++++++++\n 4 files changed, 336 insertions(+)", "diff": "diff --git a/lib/librte_pipeline/rte_pipeline_version.map b/lib/librte_pipeline/rte_pipeline_version.map\nindex a9ebd3b1f..88fd38ca8 100644\n--- a/lib/librte_pipeline/rte_pipeline_version.map\n+++ b/lib/librte_pipeline/rte_pipeline_version.map\n@@ -58,6 +58,8 @@ EXPERIMENTAL {\n \trte_swx_pipeline_config;\n \trte_swx_pipeline_port_in_type_register;\n \trte_swx_pipeline_port_in_config;\n+\trte_swx_pipeline_port_out_type_register;\n+\trte_swx_pipeline_port_out_config;\n \trte_swx_pipeline_build;\n \trte_swx_pipeline_free;\n };\ndiff --git a/lib/librte_pipeline/rte_swx_pipeline.c b/lib/librte_pipeline/rte_swx_pipeline.c\nindex 5b1559209..7aeac8cc8 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.c\n+++ b/lib/librte_pipeline/rte_swx_pipeline.c\n@@ -45,16 +45,46 @@ struct port_in_runtime {\n \tvoid *obj;\n };\n \n+/*\n+ * Output port.\n+ */\n+struct port_out_type {\n+\tTAILQ_ENTRY(port_out_type) node;\n+\tchar name[RTE_SWX_NAME_SIZE];\n+\tstruct rte_swx_port_out_ops ops;\n+};\n+\n+TAILQ_HEAD(port_out_type_tailq, port_out_type);\n+\n+struct port_out {\n+\tTAILQ_ENTRY(port_out) node;\n+\tstruct port_out_type *type;\n+\tvoid *obj;\n+\tuint32_t id;\n+};\n+\n+TAILQ_HEAD(port_out_tailq, port_out);\n+\n+struct port_out_runtime {\n+\trte_swx_port_out_pkt_tx_t pkt_tx;\n+\trte_swx_port_out_flush_t flush;\n+\tvoid *obj;\n+};\n+\n /*\n * Pipeline.\n */\n struct rte_swx_pipeline {\n \tstruct port_in_type_tailq port_in_types;\n \tstruct port_in_tailq ports_in;\n+\tstruct port_out_type_tailq port_out_types;\n+\tstruct port_out_tailq ports_out;\n \n \tstruct port_in_runtime *in;\n+\tstruct port_out_runtime *out;\n \n \tuint32_t n_ports_in;\n+\tuint32_t n_ports_out;\n \tint build_done;\n \tint numa_node;\n };\n@@ -221,6 +251,168 @@ port_in_free(struct rte_swx_pipeline *p)\n \t}\n }\n \n+/*\n+ * Output port.\n+ */\n+static struct port_out_type *\n+port_out_type_find(struct rte_swx_pipeline *p, const char *name)\n+{\n+\tstruct port_out_type *elem;\n+\n+\tif (!name)\n+\t\treturn NULL;\n+\n+\tTAILQ_FOREACH(elem, &p->port_out_types, node)\n+\t\tif (!strcmp(elem->name, name))\n+\t\t\treturn elem;\n+\n+\treturn NULL;\n+}\n+\n+int\n+rte_swx_pipeline_port_out_type_register(struct rte_swx_pipeline *p,\n+\t\t\t\t\tconst char *name,\n+\t\t\t\t\tstruct rte_swx_port_out_ops *ops)\n+{\n+\tstruct port_out_type *elem;\n+\n+\tCHECK(p, EINVAL);\n+\tCHECK_NAME(name, EINVAL);\n+\tCHECK(ops, EINVAL);\n+\tCHECK(ops->create, EINVAL);\n+\tCHECK(ops->free, EINVAL);\n+\tCHECK(ops->pkt_tx, EINVAL);\n+\tCHECK(ops->stats_read, EINVAL);\n+\n+\tCHECK(!port_out_type_find(p, name), EEXIST);\n+\n+\t/* Node allocation. */\n+\telem = calloc(1, sizeof(struct port_out_type));\n+\tCHECK(elem, ENOMEM);\n+\n+\t/* Node initialization. */\n+\tstrcpy(elem->name, name);\n+\tmemcpy(&elem->ops, ops, sizeof(*ops));\n+\n+\t/* Node add to tailq. */\n+\tTAILQ_INSERT_TAIL(&p->port_out_types, elem, node);\n+\n+\treturn 0;\n+}\n+\n+static struct port_out *\n+port_out_find(struct rte_swx_pipeline *p, uint32_t port_id)\n+{\n+\tstruct port_out *port;\n+\n+\tTAILQ_FOREACH(port, &p->ports_out, node)\n+\t\tif (port->id == port_id)\n+\t\t\treturn port;\n+\n+\treturn NULL;\n+}\n+\n+int\n+rte_swx_pipeline_port_out_config(struct rte_swx_pipeline *p,\n+\t\t\t\t uint32_t port_id,\n+\t\t\t\t const char *port_type_name,\n+\t\t\t\t void *args)\n+{\n+\tstruct port_out_type *type = NULL;\n+\tstruct port_out *port = NULL;\n+\tvoid *obj = NULL;\n+\n+\tCHECK(p, EINVAL);\n+\n+\tCHECK(!port_out_find(p, port_id), EINVAL);\n+\n+\tCHECK_NAME(port_type_name, EINVAL);\n+\ttype = port_out_type_find(p, port_type_name);\n+\tCHECK(type, EINVAL);\n+\n+\tobj = type->ops.create(args);\n+\tCHECK(obj, ENODEV);\n+\n+\t/* Node allocation. */\n+\tport = calloc(1, sizeof(struct port_out));\n+\tCHECK(port, ENOMEM);\n+\n+\t/* Node initialization. */\n+\tport->type = type;\n+\tport->obj = obj;\n+\tport->id = port_id;\n+\n+\t/* Node add to tailq. */\n+\tTAILQ_INSERT_TAIL(&p->ports_out, port, node);\n+\tif (p->n_ports_out < port_id + 1)\n+\t\tp->n_ports_out = port_id + 1;\n+\n+\treturn 0;\n+}\n+\n+static int\n+port_out_build(struct rte_swx_pipeline *p)\n+{\n+\tstruct port_out *port;\n+\tuint32_t i;\n+\n+\tCHECK(p->n_ports_out, EINVAL);\n+\n+\tfor (i = 0; i < p->n_ports_out; i++)\n+\t\tCHECK(port_out_find(p, i), EINVAL);\n+\n+\tp->out = calloc(p->n_ports_out, sizeof(struct port_out_runtime));\n+\tCHECK(p->out, ENOMEM);\n+\n+\tTAILQ_FOREACH(port, &p->ports_out, node) {\n+\t\tstruct port_out_runtime *out = &p->out[port->id];\n+\n+\t\tout->pkt_tx = port->type->ops.pkt_tx;\n+\t\tout->flush = port->type->ops.flush;\n+\t\tout->obj = port->obj;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+port_out_build_free(struct rte_swx_pipeline *p)\n+{\n+\tfree(p->out);\n+\tp->out = NULL;\n+}\n+\n+static void\n+port_out_free(struct rte_swx_pipeline *p)\n+{\n+\tport_out_build_free(p);\n+\n+\t/* Output ports. */\n+\tfor ( ; ; ) {\n+\t\tstruct port_out *port;\n+\n+\t\tport = TAILQ_FIRST(&p->ports_out);\n+\t\tif (!port)\n+\t\t\tbreak;\n+\n+\t\tTAILQ_REMOVE(&p->ports_out, port, node);\n+\t\tport->type->ops.free(port->obj);\n+\t\tfree(port);\n+\t}\n+\n+\t/* Output port types. */\n+\tfor ( ; ; ) {\n+\t\tstruct port_out_type *elem;\n+\n+\t\telem = TAILQ_FIRST(&p->port_out_types);\n+\t\tif (!elem)\n+\t\t\tbreak;\n+\n+\t\tTAILQ_REMOVE(&p->port_out_types, elem, node);\n+\t\tfree(elem);\n+\t}\n+}\n+\n /*\n * Pipeline.\n */\n@@ -239,6 +431,8 @@ rte_swx_pipeline_config(struct rte_swx_pipeline **p, int numa_node)\n \t/* Initialization. */\n \tTAILQ_INIT(&pipeline->port_in_types);\n \tTAILQ_INIT(&pipeline->ports_in);\n+\tTAILQ_INIT(&pipeline->port_out_types);\n+\tTAILQ_INIT(&pipeline->ports_out);\n \n \tpipeline->numa_node = numa_node;\n \n@@ -252,6 +446,7 @@ rte_swx_pipeline_free(struct rte_swx_pipeline *p)\n \tif (!p)\n \t\treturn;\n \n+\tport_out_free(p);\n \tport_in_free(p);\n \n \tfree(p);\n@@ -269,10 +464,15 @@ rte_swx_pipeline_build(struct rte_swx_pipeline *p)\n \tif (status)\n \t\tgoto error;\n \n+\tstatus = port_out_build(p);\n+\tif (status)\n+\t\tgoto error;\n+\n \tp->build_done = 1;\n \treturn 0;\n \n error:\n+\tport_out_build_free(p);\n \tport_in_build_free(p);\n \n \treturn status;\ndiff --git a/lib/librte_pipeline/rte_swx_pipeline.h b/lib/librte_pipeline/rte_swx_pipeline.h\nindex 3dbe7ce0b..2be83bd35 100644\n--- a/lib/librte_pipeline/rte_swx_pipeline.h\n+++ b/lib/librte_pipeline/rte_swx_pipeline.h\n@@ -97,6 +97,56 @@ rte_swx_pipeline_port_in_config(struct rte_swx_pipeline *p,\n \t\t\t\tuint32_t port_id,\n \t\t\t\tconst char *port_type_name,\n \t\t\t\tvoid *args);\n+\n+/*\n+ * Pipeline output ports\n+ */\n+\n+/**\n+ * Pipeline output port type register\n+ *\n+ * @param[in] p\n+ * Pipeline handle.\n+ * @param[in] name\n+ * Output port type name.\n+ * @param[in] ops\n+ * Output port type operations.\n+ * @return\n+ * 0 on success or the following error codes otherwise:\n+ * -EINVAL: Invalid argument;\n+ * -ENOMEM: Not enough space/cannot allocate memory;\n+ * -EEXIST: Output port type with this name already exists.\n+ */\n+__rte_experimental\n+int\n+rte_swx_pipeline_port_out_type_register(struct rte_swx_pipeline *p,\n+\t\t\t\t\tconst char *name,\n+\t\t\t\t\tstruct rte_swx_port_out_ops *ops);\n+\n+/**\n+ * Pipeline output port configure\n+ *\n+ * @param[in] p\n+ * Pipeline handle.\n+ * @param[in] port_id\n+ * Output port ID.\n+ * @param[in] port_type_name\n+ * Existing output port type name.\n+ * @param[in] args\n+ * Output port creation arguments.\n+ * @return\n+ * 0 on success or the following error codes otherwise:\n+ * -EINVAL: Invalid argument;\n+ * -ENOMEM: Not enough space/cannot allocate memory;\n+ * -ENODEV: Output port object creation error.\n+ */\n+__rte_experimental\n+int\n+rte_swx_pipeline_port_out_config(struct rte_swx_pipeline *p,\n+\t\t\t\t uint32_t port_id,\n+\t\t\t\t const char *port_type_name,\n+\t\t\t\t void *args);\n+\n /**\n * Pipeline build\n *\ndiff --git a/lib/librte_port/rte_swx_port.h b/lib/librte_port/rte_swx_port.h\nindex a6f80de9a..4beb59991 100644\n--- a/lib/librte_port/rte_swx_port.h\n+++ b/lib/librte_port/rte_swx_port.h\n@@ -111,6 +111,90 @@ struct rte_swx_port_in_ops {\n \trte_swx_port_in_stats_read_t stats_read;\n };\n \n+/*\n+ * Output port\n+ */\n+\n+/**\n+ * Output port create\n+ *\n+ * @param[in] args\n+ * Arguments for output port creation. Format specific to each port type.\n+ * @return\n+ * Handle to output port instance on success, NULL on error.\n+ */\n+typedef void *\n+(*rte_swx_port_out_create_t)(void *args);\n+\n+/**\n+ * Output port free\n+ *\n+ * @param[in] args\n+ * Output port handle.\n+ */\n+typedef void\n+(*rte_swx_port_out_free_t)(void *port);\n+\n+/**\n+ * Output port packet transmit\n+ *\n+ * @param[in] port\n+ * Output port handle.\n+ * @param[in] pkt\n+ * Packet to be transmitted.\n+ */\n+typedef void\n+(*rte_swx_port_out_pkt_tx_t)(void *port,\n+\t\t\t struct rte_swx_pkt *pkt);\n+\n+/**\n+ * Output port flush\n+ *\n+ * @param[in] port\n+ * Output port handle.\n+ */\n+typedef void\n+(*rte_swx_port_out_flush_t)(void *port);\n+\n+/** Output port statistics counters. */\n+struct rte_swx_port_out_stats {\n+\t/** Number of packets. */\n+\tuint64_t n_pkts;\n+\n+\t/** Number of bytes. */\n+\tuint64_t n_bytes;\n+};\n+\n+/**\n+ * Output port statistics counters read\n+ *\n+ * @param[in] port\n+ * Output port handle.\n+ * @param[out] stats\n+ * Output port statistics counters. Must point to valid memory.\n+ */\n+typedef void\n+(*rte_swx_port_out_stats_read_t)(void *port,\n+\t\t\t\t struct rte_swx_port_out_stats *stats);\n+\n+/** Output port operations. */\n+struct rte_swx_port_out_ops {\n+\t/** Create. Must be non-NULL. */\n+\trte_swx_port_out_create_t create;\n+\n+\t/** Free. Must be non-NULL. */\n+\trte_swx_port_out_free_t free;\n+\n+\t/** Packet transmission. Must be non-NULL. */\n+\trte_swx_port_out_pkt_tx_t pkt_tx;\n+\n+\t/** Flush. May be NULL. */\n+\trte_swx_port_out_flush_t flush;\n+\n+\t/** Statistics counters read. Must be non-NULL. */\n+\trte_swx_port_out_stats_read_t stats_read;\n+};\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "v3", "03/41" ] }