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{
    "id": 76911,
    "url": "http://patches.dpdk.org/api/patches/76911/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200908100956.25868-3-adwivedi@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200908100956.25868-3-adwivedi@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200908100956.25868-3-adwivedi@marvell.com",
    "date": "2020-09-08T10:09:55",
    "name": "[2/3] event/octeontx2: add crypto adapter framework",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "793950d524eebbe1f7d2a86956b5fcd081d42e05",
    "submitter": {
        "id": 1561,
        "url": "http://patches.dpdk.org/api/people/1561/?format=api",
        "name": "Ankur Dwivedi",
        "email": "adwivedi@marvell.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200908100956.25868-3-adwivedi@marvell.com/mbox/",
    "series": [
        {
            "id": 12021,
            "url": "http://patches.dpdk.org/api/series/12021/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=12021",
            "date": "2020-09-08T10:09:53",
            "name": "event/octeontx2: add support for event crypto adapter",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/12021/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/76911/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/76911/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 982AF1C0CE;\n\tTue,  8 Sep 2020 12:10:44 +0200 (CEST)",
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        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=IL9QhcwUTP2jiAq/x3C+yB4jbDToGunynREZzVTVHyk=;\n b=hMdIy8DjnyyM6akHoZtABF2SRra4svUkNq17YIZWNbt/l8GcXDjhQdGAdWzldyv7tqS/\n 8l2I2ePN5z72Lg5YOfopW2MWD9KlIHURRyuj2B28Kd8Y2hiQYd4uq42zvTEDfHwWTfyq\n TXxcPkG7IH9HAKbazeOEuQaVxn+gHOUiZ7QRw0SLK1S+S24UBOkrDpRGg7z5Ekp0lWKa\n VuGdG8+2nF7kwp1DLFgFmNlf+Ou7RFndX5Y1rb2bmAvxMVuwPRPVgBMSS+Qmp6f/ySqS\n YOP3Au/442R4U6raTXjdqqGz8ScW6yg8Dz6U8idiMSDPIzkBa0Lp006DjNE4AWHy7sgs 3w==",
        "From": "Ankur Dwivedi <adwivedi@marvell.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<jerinj@marvell.com>, <pbhagavatula@marvell.com>, <akhil.goyal@nxp.com>,\n <anoobj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>",
        "Date": "Tue, 8 Sep 2020 15:39:55 +0530",
        "Message-ID": "<20200908100956.25868-3-adwivedi@marvell.com>",
        "X-Mailer": "git-send-email 2.28.0",
        "In-Reply-To": "<20200908100956.25868-1-adwivedi@marvell.com>",
        "References": "<20200908100956.25868-1-adwivedi@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-09-08_05:2020-09-08,\n 2020-09-08 signatures=0",
        "Subject": "[dpdk-dev] [PATCH 2/3] event/octeontx2: add crypto adapter framework",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The crypto adapter callback functions and associated data structures\nare added.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\n---\n drivers/crypto/octeontx2/meson.build          |  4 +-\n .../crypto/octeontx2/otx2_crypto_adapter.c    | 77 +++++++++++++++++++\n .../crypto/octeontx2/otx2_crypto_adapter.h    | 21 +++++\n .../octeontx2/otx2_cryptodev_hw_access.h      | 12 +++\n drivers/crypto/octeontx2/otx2_cryptodev_qp.h  |  7 ++\n .../rte_pmd_octeontx2_crypto_version.map      | 10 +++\n drivers/event/octeontx2/meson.build           |  2 +-\n drivers/event/octeontx2/otx2_evdev.c          |  5 ++\n 8 files changed, 136 insertions(+), 2 deletions(-)\n create mode 100644 drivers/crypto/octeontx2/otx2_crypto_adapter.c\n create mode 100644 drivers/crypto/octeontx2/otx2_crypto_adapter.h",
    "diff": "diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build\nindex 148ec184a..063a553f2 100644\n--- a/drivers/crypto/octeontx2/meson.build\n+++ b/drivers/crypto/octeontx2/meson.build\n@@ -10,6 +10,7 @@ deps += ['bus_pci']\n deps += ['common_cpt']\n deps += ['common_octeontx2']\n deps += ['ethdev']\n+deps += ['eventdev']\n deps += ['security']\n name = 'octeontx2_crypto'\n \n@@ -18,7 +19,8 @@ sources = files('otx2_cryptodev.c',\n \t\t'otx2_cryptodev_hw_access.c',\n \t\t'otx2_cryptodev_mbox.c',\n \t\t'otx2_cryptodev_ops.c',\n-\t\t'otx2_cryptodev_sec.c')\n+\t\t'otx2_cryptodev_sec.c',\n+\t\t'otx2_crypto_adapter.c')\n \n extra_flags = []\n # This integrated controller runs only on a arm64 machine, remove 32bit warnings\ndiff --git a/drivers/crypto/octeontx2/otx2_crypto_adapter.c b/drivers/crypto/octeontx2/otx2_crypto_adapter.c\nnew file mode 100644\nindex 000000000..cfde7ec4f\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_crypto_adapter.c\n@@ -0,0 +1,77 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <rte_eventdev.h>\n+\n+#include \"otx2_cryptodev_hw_access.h\"\n+#include \"otx2_cryptodev_qp.h\"\n+#include \"otx2_cryptodev_mbox.h\"\n+#include \"otx2_crypto_adapter.h\"\n+\n+int\n+otx2_ca_caps_get(const struct rte_eventdev *dev,\n+\t\tconst struct rte_cryptodev *cdev, uint32_t *caps)\n+{\n+\tRTE_SET_USED(dev);\n+\tRTE_SET_USED(cdev);\n+\n+\t*caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND |\n+\t\tRTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n+\t\tint32_t queue_pair_id, const struct rte_event *event)\n+{\n+\tunion otx2_cpt_af_lf_ctl2 af_lf_ctl2;\n+\tstruct otx2_cpt_qp *qp;\n+\tint ret;\n+\n+\tRTE_SET_USED(dev);\n+\n+\tqp = cdev->data->queue_pairs[queue_pair_id];\n+\n+\tqp->ca_enable = 1;\n+\trte_memcpy(&qp->ev, event, sizeof(struct rte_event));\n+\n+\tret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n+\t\t\t&af_lf_ctl2.u);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\taf_lf_ctl2.s.sso_pf_func = otx2_sso_pf_func_get();\n+\tret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n+\t\t\taf_lf_ctl2.u);\n+\n+\treturn ret;\n+}\n+\n+int\n+otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n+\t\tint32_t queue_pair_id)\n+{\n+\tunion otx2_cpt_af_lf_ctl2 af_lf_ctl2;\n+\tstruct otx2_cpt_qp *qp;\n+\tint ret;\n+\n+\tRTE_SET_USED(dev);\n+\n+\tqp = cdev->data->queue_pairs[queue_pair_id];\n+\tqp->ca_enable = 0;\n+\tmemset(&qp->ev, 0, sizeof(struct rte_event));\n+\n+\tret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n+\t\t\t&af_lf_ctl2.u);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\taf_lf_ctl2.s.sso_pf_func = 0;\n+\tret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n+\t\t\taf_lf_ctl2.u);\n+\n+\treturn ret;\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_crypto_adapter.h b/drivers/crypto/octeontx2/otx2_crypto_adapter.h\nnew file mode 100644\nindex 000000000..c8f02c0af\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_crypto_adapter.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2020 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_CRYPTO_ADAPTER_H_\n+#define _OTX2_CRYPTO_ADAPTER_H_\n+\n+__rte_internal\n+int otx2_ca_caps_get(const struct rte_eventdev *dev,\n+\t\tconst struct rte_cryptodev *cdev, uint32_t *caps);\n+\n+__rte_internal\n+int otx2_ca_qp_add(const struct rte_eventdev *dev,\n+\t\tconst struct rte_cryptodev *cdev, int32_t queue_pair_id,\n+\t\tconst struct rte_event *event);\n+\n+__rte_internal\n+int otx2_ca_qp_del(const struct rte_eventdev *dev,\n+\t\tconst struct rte_cryptodev *cdev, int32_t queue_pair_id);\n+\n+#endif /* _OTX2_CRYPTO_ADAPTER_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\nindex 43db6a642..a435818e0 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n@@ -42,6 +42,7 @@\n #define OTX2_CPT_LF_NQ(a)\t\t(0x400ull | (uint64_t)(a) << 3)\n \n #define OTX2_CPT_AF_LF_CTL(a)\t\t(0x27000ull | (uint64_t)(a) << 3)\n+#define OTX2_CPT_AF_LF_CTL2(a)\t\t(0x29000ull | (uint64_t)(a) << 3)\n \n #define OTX2_CPT_LF_BAR2(vf, q_id) \\\n \t\t((vf)->otx2_dev.bar2 + \\\n@@ -110,6 +111,17 @@ union otx2_cpt_af_lf_ctl {\n \t} s;\n };\n \n+union otx2_cpt_af_lf_ctl2 {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t exe_no_swap                 : 1;\n+\t\tuint64_t exe_ldwb                    : 1;\n+\t\tuint64_t reserved_2_31               : 30;\n+\t\tuint64_t sso_pf_func                 : 16;\n+\t\tuint64_t nix_pf_func                 : 16;\n+\t} s;\n+};\n+\n union otx2_cpt_lf_q_grp_ptr {\n \tuint64_t u;\n \tstruct {\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\nindex 9d48da45f..96ff4eb41 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n@@ -6,6 +6,7 @@\n #define _OTX2_CRYPTODEV_QP_H_\n \n #include <rte_common.h>\n+#include <rte_eventdev.h>\n #include <rte_mempool.h>\n #include <rte_spinlock.h>\n \n@@ -30,6 +31,12 @@ struct otx2_cpt_qp {\n \t/**< Metabuf info required to support operations on the queue pair */\n \trte_iova_t iq_dma_addr;\n \t/**< Instruction queue address */\n+\tstruct rte_event ev;\n+\t/**< Event information required for binding cryptodev queue to\n+\t * eventdev queue. Used by crypto adapter.\n+\t */\n+\tuint8_t ca_enable;\n+\t/**< Set when queue pair is added to crypto adapter */\n };\n \n #endif /* _OTX2_CRYPTODEV_QP_H_ */\ndiff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\nindex 4a76d1d52..b47a7ad3e 100644\n--- a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\n+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\n@@ -1,3 +1,13 @@\n DPDK_21 {\n \tlocal: *;\n };\n+\n+INTERNAL {\n+\tglobal:\n+\n+\totx2_ca_caps_get;\n+\totx2_ca_qp_add;\n+\totx2_ca_qp_del;\n+\n+\tlocal: *;\n+};\ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\nindex 0ade51cec..8585c54e4 100644\n--- a/drivers/event/octeontx2/meson.build\n+++ b/drivers/event/octeontx2/meson.build\n@@ -24,6 +24,6 @@ foreach flag: extra_flags\n \tendif\n endforeach\n \n-deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2']\n+deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2', 'pmd_octeontx2_crypto']\n \n includes += include_directories('../../crypto/octeontx2')\ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex b8b57c388..fe21787b6 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -12,6 +12,7 @@\n #include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n \n+#include \"otx2_crypto_adapter.h\"\n #include \"otx2_evdev_stats.h\"\n #include \"otx2_evdev.h\"\n #include \"otx2_irq.h\"\n@@ -1587,6 +1588,10 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \n \t.timer_adapter_caps_get = otx2_tim_caps_get,\n \n+\t.crypto_adapter_caps_get = otx2_ca_caps_get,\n+\t.crypto_adapter_queue_pair_add = otx2_ca_qp_add,\n+\t.crypto_adapter_queue_pair_del = otx2_ca_qp_del,\n+\n \t.xstats_get       = otx2_sso_xstats_get,\n \t.xstats_reset     = otx2_sso_xstats_reset,\n \t.xstats_get_names = otx2_sso_xstats_get_names,\n",
    "prefixes": [
        "2/3"
    ]
}