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GET /api/patches/76098/?format=api
http://patches.dpdk.org/api/patches/76098/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200827161304.32300-3-ciara.power@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200827161304.32300-3-ciara.power@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200827161304.32300-3-ciara.power@intel.com", "date": "2020-08-27T16:12:49", "name": "[v2,02/17] eal: add default SIMD bitwidth values", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e5c2a9d23d372ab79261dccfa45eb84b257b9ee5", "submitter": { "id": 978, "url": "http://patches.dpdk.org/api/people/978/?format=api", "name": "Power, Ciara", "email": "ciara.power@intel.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200827161304.32300-3-ciara.power@intel.com/mbox/", "series": [ { "id": 11831, "url": "http://patches.dpdk.org/api/series/11831/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11831", "date": "2020-08-27T16:12:47", "name": "add max SIMD bitwidth to EAL", "version": 2, "mbox": "http://patches.dpdk.org/series/11831/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/76098/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/76098/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DEF71A04B1;\n\tThu, 27 Aug 2020 18:13:43 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 31B551C0AD;\n\tThu, 27 Aug 2020 18:13:40 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id 781F31C065\n for <dev@dpdk.org>; Thu, 27 Aug 2020 18:13:38 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Aug 2020 09:13:18 -0700", "from silpixa00399953.ir.intel.com (HELO\n silpixa00399953.ger.corp.intel.com) ([10.237.222.53])\n by fmsmga007.fm.intel.com with ESMTP; 27 Aug 2020 09:13:16 -0700" ], "IronPort-SDR": [ "\n IU6OZvw/xGs+bwx0K08VTHWywdlmQqBoxONigQ9gWeqLlyhSK6DTBWp3wCHP6Cx81YgenHUzrt\n 6sslT3QEZDMw==", "\n 6b4fTcO4BdcnuCug6/uUtxSzSQbxRfk4OHYm+2UKGGExW8PHHoRTJUbyuYc7MHsa8JgrjZyO62\n Tr7R3OB8D2Wg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9726\"; a=\"220766987\"", "E=Sophos;i=\"5.76,360,1592895600\"; d=\"scan'208\";a=\"220766987\"", "E=Sophos;i=\"5.76,360,1592895600\"; d=\"scan'208\";a=\"280681436\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Ciara Power <ciara.power@intel.com>", "To": "dev@dpdk.org", "Cc": "Ciara Power <ciara.power@intel.com>, Ruifeng Wang <ruifeng.wang@arm.com>,\n Jerin Jacob <jerinj@marvell.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n David Christensen <drc@linux.vnet.ibm.com>,\n Jan Viktorin <viktorin@rehivetech.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>", "Date": "Thu, 27 Aug 2020 17:12:49 +0100", "Message-Id": "<20200827161304.32300-3-ciara.power@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200827161304.32300-1-ciara.power@intel.com>", "References": "<20200807155859.63888-1-ciara.power@intel.com>\n <20200827161304.32300-1-ciara.power@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 02/17] eal: add default SIMD bitwidth values", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Each arch has a define for the default SIMD bitwidth value, this is used\non EAL init to set the config max SIMD bitwidth.\n\nCc: Ruifeng Wang <ruifeng.wang@arm.com>\nCc: Jerin Jacob <jerinj@marvell.com>\nCc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nCc: David Christensen <drc@linux.vnet.ibm.com>\n\nSigned-off-by: Ciara Power <ciara.power@intel.com>\n\n---\nv2: Changed default bitwidth for Arm to 128.\n---\n lib/librte_eal/arm/include/rte_vect.h | 2 ++\n lib/librte_eal/common/eal_common_options.c | 3 +++\n lib/librte_eal/include/generic/rte_vect.h | 2 ++\n lib/librte_eal/ppc/include/rte_vect.h | 2 ++\n lib/librte_eal/x86/include/rte_vect.h | 2 ++\n 5 files changed, 11 insertions(+)", "diff": "diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h\nindex 01c51712a1..2cd61d6279 100644\n--- a/lib/librte_eal/arm/include/rte_vect.h\n+++ b/lib/librte_eal/arm/include/rte_vect.h\n@@ -14,6 +14,8 @@\n extern \"C\" {\n #endif\n \n+#define RTE_DEFAULT_SIMD_BITWIDTH 128\n+\n typedef int32x4_t xmm_t;\n \n #define\tXMM_SIZE\t(sizeof(xmm_t))\ndiff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c\nindex 90f4e8f5c3..c2a9624f89 100644\n--- a/lib/librte_eal/common/eal_common_options.c\n+++ b/lib/librte_eal/common/eal_common_options.c\n@@ -35,6 +35,7 @@\n #ifndef RTE_EXEC_ENV_WINDOWS\n #include <rte_telemetry.h>\n #endif\n+#include <rte_vect.h>\n \n #include \"eal_internal_cfg.h\"\n #include \"eal_options.h\"\n@@ -344,6 +345,8 @@ eal_reset_internal_config(struct internal_config *internal_cfg)\n \tinternal_cfg->user_mbuf_pool_ops_name = NULL;\n \tCPU_ZERO(&internal_cfg->ctrl_cpuset);\n \tinternal_cfg->init_complete = 0;\n+\tinternal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH;\n+\tinternal_cfg->max_simd_bitwidth.locked = 0;\n }\n \n static int\ndiff --git a/lib/librte_eal/include/generic/rte_vect.h b/lib/librte_eal/include/generic/rte_vect.h\nindex 3fc47979f8..e98f184a97 100644\n--- a/lib/librte_eal/include/generic/rte_vect.h\n+++ b/lib/librte_eal/include/generic/rte_vect.h\n@@ -14,6 +14,8 @@\n \n #include <stdint.h>\n \n+#define RTE_DEFAULT_SIMD_BITWIDTH 256\n+\n /* Unsigned vector types */\n \n /**\ndiff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h\nindex b0545c878c..70fbd0c423 100644\n--- a/lib/librte_eal/ppc/include/rte_vect.h\n+++ b/lib/librte_eal/ppc/include/rte_vect.h\n@@ -15,6 +15,8 @@\n extern \"C\" {\n #endif\n \n+#define RTE_DEFAULT_SIMD_BITWIDTH 256\n+\n typedef vector signed int xmm_t;\n \n #define\tXMM_SIZE\t(sizeof(xmm_t))\ndiff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h\nindex df5a607623..b1df75aca7 100644\n--- a/lib/librte_eal/x86/include/rte_vect.h\n+++ b/lib/librte_eal/x86/include/rte_vect.h\n@@ -35,6 +35,8 @@\n extern \"C\" {\n #endif\n \n+#define RTE_DEFAULT_SIMD_BITWIDTH 256\n+\n typedef __m128i xmm_t;\n \n #define\tXMM_SIZE\t(sizeof(xmm_t))\n", "prefixes": [ "v2", "02/17" ] }{ "id": 76098, "url": "