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GET /api/patches/75974/?format=api
{ "id": 75974, "url": "http://patches.dpdk.org/api/patches/75974/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200826075501.50052-2-guinanx.sun@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200826075501.50052-2-guinanx.sun@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200826075501.50052-2-guinanx.sun@intel.com", "date": "2020-08-26T07:54:55", "name": "[1/7] net/ice: change RSS hash parsing in AVX path", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "872161d994b4395d60c72d8dbbd3d43d39574203", "submitter": { "id": 1476, "url": "http://patches.dpdk.org/api/people/1476/?format=api", "name": "Guinan Sun", "email": "guinanx.sun@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200826075501.50052-2-guinanx.sun@intel.com/mbox/", "series": [ { "id": 11796, "url": "http://patches.dpdk.org/api/series/11796/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11796", "date": "2020-08-26T07:54:54", "name": "support RXDID22 and FDID22", "version": 1, "mbox": "http://patches.dpdk.org/series/11796/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/75974/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/75974/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CEE06A04B1;\n\tWed, 26 Aug 2020 10:13:36 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6232A1C0B3;\n\tWed, 26 Aug 2020 10:13:31 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by dpdk.org (Postfix) with ESMTP id 693F41C0AD\n for <dev@dpdk.org>; Wed, 26 Aug 2020 10:13:28 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Aug 2020 01:13:28 -0700", "from dpdk.sh.intel.com ([10.239.255.12])\n by orsmga002.jf.intel.com with ESMTP; 26 Aug 2020 01:13:26 -0700" ], "IronPort-SDR": [ "\n vOa0q+XjQClbzpozVcjrSo0hBK0KqwAY+grF87Hf48d+K9W61L8nV/Fc0GMmWWEBu15bI6Gm4n\n L2UFKw10UQjA==", "\n BkG39SKPJlDTAEZfdBNY6fhMkYW49XR3m/p3tsPL1yLmiTT/pzsO8KhqsBuFUgW6ybAwSFcpaB\n Njxdao1AuE7Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9724\"; a=\"155512873\"", "E=Sophos;i=\"5.76,354,1592895600\"; d=\"scan'208\";a=\"155512873\"", "E=Sophos;i=\"5.76,354,1592895600\"; d=\"scan'208\";a=\"312816176\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Guinan Sun <guinanx.sun@intel.com>", "To": "dev@dpdk.org", "Cc": "Qi Zhang <qi.z.zhang@intel.com>, Qiming Yang <qiming.yang@intel.com>,\n Junyu Jiang <junyux.jiang@intel.com>", "Date": "Wed, 26 Aug 2020 07:54:55 +0000", "Message-Id": "<20200826075501.50052-2-guinanx.sun@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200826075501.50052-1-guinanx.sun@intel.com>", "References": "<20200826075501.50052-1-guinanx.sun@intel.com>", "Subject": "[dpdk-dev] [PATCH 1/7] net/ice: change RSS hash parsing in AVX path", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Junyu Jiang <junyux.jiang@intel.com>\n\nChange RSS hash parsing from Flex Rx descriptor in AVX data path.\n\nSigned-off-by: Junyu Jiang <junyux.jiang@intel.com>\n---\n drivers/net/ice/ice_rxtx_vec_avx2.c | 98 +++++++++++++++++++++++++++--\n 1 file changed, 94 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c b/drivers/net/ice/ice_rxtx_vec_avx2.c\nindex be50677c2..07d129e3f 100644\n--- a/drivers/net/ice/ice_rxtx_vec_avx2.c\n+++ b/drivers/net/ice/ice_rxtx_vec_avx2.c\n@@ -191,8 +191,8 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \tconst __m256i shuf_msk =\n \t\t_mm256_set_epi8\n \t\t\t(/* first descriptor */\n-\t\t\t 15, 14,\n-\t\t\t 13, 12,\t/* octet 12~15, 32 bits rss */\n+\t\t\t 0xFF, 0xFF,\n+\t\t\t 0xFF, 0xFF,\t/* rss hash parsed separately */\n \t\t\t 11, 10,\t/* octet 10~11, 16 bits vlan_macip */\n \t\t\t 5, 4,\t\t/* octet 4~5, 16 bits data_len */\n \t\t\t 0xFF, 0xFF,\t/* skip hi 16 bits pkt_len, zero out */\n@@ -200,8 +200,8 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t\t 0xFF, 0xFF,\t/* pkt_type set as unknown */\n \t\t\t 0xFF, 0xFF,\t/*pkt_type set as unknown */\n \t\t\t /* second descriptor */\n-\t\t\t 15, 14,\n-\t\t\t 13, 12,\t/* octet 12~15, 32 bits rss */\n+\t\t\t 0xFF, 0xFF,\n+\t\t\t 0xFF, 0xFF,\t/* rss hash parsed separately */\n \t\t\t 11, 10,\t/* octet 10~11, 16 bits vlan_macip */\n \t\t\t 5, 4,\t\t/* octet 4~5, 16 bits data_len */\n \t\t\t 0xFF, 0xFF,\t/* skip hi 16 bits pkt_len, zero out */\n@@ -461,6 +461,96 @@ _ice_recv_raw_pkts_vec_avx2(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,\n \t\t/* merge flags */\n \t\tconst __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,\n \t\t\t\trss_vlan_flags);\n+\n+#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+\t\t/**\n+\t\t * needs to load 2nd 16B of each desc for RSS hash parsing,\n+\t\t * will cause performance drop to get into this context.\n+\t\t */\n+\t\tif (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &\n+\t\t\t\tDEV_RX_OFFLOAD_RSS_HASH) {\n+\t\t\t/* load bottom half of every 32B desc */\n+\t\t\tconst __m128i raw_desc_bh7 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[7].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh6 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[6].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh5 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[5].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh4 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[4].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh3 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[3].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh2 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[2].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh1 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[1].wb.status_error1));\n+\t\t\trte_compiler_barrier();\n+\t\t\tconst __m128i raw_desc_bh0 =\n+\t\t\t\t_mm_load_si128\n+\t\t\t\t\t((void *)(&rxdp[0].wb.status_error1));\n+\n+\t\t\t__m256i raw_desc_bh6_7 =\n+\t\t\t\t_mm256_inserti128_si256\n+\t\t\t\t\t(_mm256_castsi128_si256(raw_desc_bh6),\n+\t\t\t\t\traw_desc_bh7, 1);\n+\t\t\t__m256i raw_desc_bh4_5 =\n+\t\t\t\t_mm256_inserti128_si256\n+\t\t\t\t\t(_mm256_castsi128_si256(raw_desc_bh4),\n+\t\t\t\t\traw_desc_bh5, 1);\n+\t\t\t__m256i raw_desc_bh2_3 =\n+\t\t\t\t_mm256_inserti128_si256\n+\t\t\t\t\t(_mm256_castsi128_si256(raw_desc_bh2),\n+\t\t\t\t\traw_desc_bh3, 1);\n+\t\t\t__m256i raw_desc_bh0_1 =\n+\t\t\t\t_mm256_inserti128_si256\n+\t\t\t\t\t(_mm256_castsi128_si256(raw_desc_bh0),\n+\t\t\t\t\traw_desc_bh1, 1);\n+\n+\t\t\t/**\n+\t\t\t * to shift the 32b RSS hash value to the\n+\t\t\t * highest 32b of each 128b before mask\n+\t\t\t */\n+\t\t\t__m256i rss_hash6_7 =\n+\t\t\t\t_mm256_slli_epi64(raw_desc_bh6_7, 32);\n+\t\t\t__m256i rss_hash4_5 =\n+\t\t\t\t_mm256_slli_epi64(raw_desc_bh4_5, 32);\n+\t\t\t__m256i rss_hash2_3 =\n+\t\t\t\t_mm256_slli_epi64(raw_desc_bh2_3, 32);\n+\t\t\t__m256i rss_hash0_1 =\n+\t\t\t\t_mm256_slli_epi64(raw_desc_bh0_1, 32);\n+\n+\t\t\t__m256i rss_hash_msk =\n+\t\t\t\t_mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,\n+\t\t\t\t\t\t 0xFFFFFFFF, 0, 0, 0);\n+\n+\t\t\trss_hash6_7 = _mm256_and_si256\n+\t\t\t\t\t(rss_hash6_7, rss_hash_msk);\n+\t\t\trss_hash4_5 = _mm256_and_si256\n+\t\t\t\t\t(rss_hash4_5, rss_hash_msk);\n+\t\t\trss_hash2_3 = _mm256_and_si256\n+\t\t\t\t\t(rss_hash2_3, rss_hash_msk);\n+\t\t\trss_hash0_1 = _mm256_and_si256\n+\t\t\t\t\t(rss_hash0_1, rss_hash_msk);\n+\n+\t\t\tmb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);\n+\t\t\tmb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);\n+\t\t\tmb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);\n+\t\t\tmb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);\n+\t\t} /* if() on RSS hash parsing */\n+#endif\n \t\t/**\n \t\t * At this point, we have the 8 sets of flags in the low 16-bits\n \t\t * of each 32-bit value in vlan0.\n", "prefixes": [ "1/7" ] }