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GET /api/patches/75900/?format=api
{ "id": 75900, "url": "http://patches.dpdk.org/api/patches/75900/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200825093116.26538-3-ophirmu@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200825093116.26538-3-ophirmu@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200825093116.26538-3-ophirmu@nvidia.com", "date": "2020-08-25T09:31:05", "name": "[v2,02/13] common/mlx5: replace Linux __bexx types with rte", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7b0cb1483590f701103527217507afbfaeaeea5a", "submitter": { "id": 1908, "url": "http://patches.dpdk.org/api/people/1908/?format=api", "name": "Ophir Munk", "email": "ophirmu@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200825093116.26538-3-ophirmu@nvidia.com/mbox/", "series": [ { "id": 11773, "url": "http://patches.dpdk.org/api/series/11773/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11773", "date": "2020-08-25T09:31:06", "name": "mlx5 PMD multi OS support - part #4", "version": 2, "mbox": "http://patches.dpdk.org/series/11773/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/75900/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/75900/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 96C35A04B1;\n\tTue, 25 Aug 2020 11:31:46 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 00F6A1C1B9;\n\tTue, 25 Aug 2020 11:31:34 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id A01531C1A8\n for <dev@dpdk.org>; Tue, 25 Aug 2020 11:31:29 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n ophirmu@nvidia.com) with SMTP; 25 Aug 2020 12:31:25 +0300", "from nvidia.com (pegasus05.mtr.labs.mlnx [10.210.16.100])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 07P9VPMq030009;\n Tue, 25 Aug 2020 12:31:25 +0300" ], "From": "Ophir Munk <ophirmu@nvidia.com>", "To": "dev@dpdk.org", "Cc": "Ophir Munk <ophirmu@mellanox.com>", "Date": "Tue, 25 Aug 2020 09:31:05 +0000", "Message-Id": "<20200825093116.26538-3-ophirmu@nvidia.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20200825093116.26538-1-ophirmu@nvidia.com>", "References": "<20200820145028.4090-1-ophirmu@nvidia.com>\n <20200825093116.26538-1-ophirmu@nvidia.com>", "Subject": "[dpdk-dev] [PATCH v2 02/13] common/mlx5: replace Linux __bexx types\n\twith rte", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ophir Munk <ophirmu@mellanox.com>\n\nReplace Linux specific int types with their corresponding rte typedefs.\n__be16 ==> rte_be16_t\n__be32 ==> rte_be32_t\n__be64 ==> rte_be64_t\n\nSigned-off-by: Ophir Munk <ophirmu@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 14 +++++++-------\n 1 file changed, 7 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex e0ebe12..69511bc 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -608,7 +608,7 @@ typedef uint8_t u8;\n #define MLX5_SET(typ, p, fld, v) \\\n \tdo { \\\n \t\tu32 _v = v; \\\n-\t\t*((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \\\n+\t\t*((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \\\n \t\trte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \\\n \t\t\t\t __mlx5_dw_off(typ, fld))) & \\\n \t\t\t\t (~__mlx5_dw_mask(typ, fld))) | \\\n@@ -619,15 +619,15 @@ typedef uint8_t u8;\n #define MLX5_SET64(typ, p, fld, v) \\\n \tdo { \\\n \t\tMLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \\\n-\t\t*((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \\\n+\t\t*((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \\\n \t\t\trte_cpu_to_be_64(v); \\\n \t} while (0)\n \n #define MLX5_SET16(typ, p, fld, v) \\\n \tdo { \\\n \t\tu16 _v = v; \\\n-\t\t*((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \\\n-\t\trte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \\\n+\t\t*((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \\\n+\t\trte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \\\n \t\t\t\t __mlx5_16_off(typ, fld))) & \\\n \t\t\t\t (~__mlx5_16_mask(typ, fld))) | \\\n \t\t\t\t (((_v) & __mlx5_mask16(typ, fld)) << \\\n@@ -639,14 +639,14 @@ typedef uint8_t u8;\n \t__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \\\n \t__mlx5_mask(typ, fld))\n #define MLX5_GET(typ, p, fld) \\\n-\t((rte_be_to_cpu_32(*((__be32 *)(p) +\\\n+\t((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\\\n \t__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \\\n \t__mlx5_mask(typ, fld))\n #define MLX5_GET16(typ, p, fld) \\\n-\t((rte_be_to_cpu_16(*((__be16 *)(p) + \\\n+\t((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \\\n \t __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \\\n \t __mlx5_mask16(typ, fld))\n-#define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \\\n+#define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \\\n \t\t\t\t\t\t __mlx5_64_off(typ, fld)))\n #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)\n \n", "prefixes": [ "v2", "02/13" ] }