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GET /api/patches/74882/?format=api
{ "id": 74882, "url": "http://patches.dpdk.org/api/patches/74882/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200727220341.29084-5-manishc@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200727220341.29084-5-manishc@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200727220341.29084-5-manishc@marvell.com", "date": "2020-07-27T22:03:39", "name": "[v4,4/6] net/qede: add infrastructure support for VF load", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7c6390927c05cb580a3bf9575d722d903b90e385", "submitter": { "id": 1591, "url": "http://patches.dpdk.org/api/people/1591/?format=api", "name": "Manish Chopra", "email": "manishc@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200727220341.29084-5-manishc@marvell.com/mbox/", "series": [ { "id": 11335, "url": "http://patches.dpdk.org/api/series/11335/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11335", "date": "2020-07-27T22:03:35", "name": "qede: SR-IOV PF driver support", "version": 4, "mbox": "http://patches.dpdk.org/series/11335/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74882/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/74882/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7EA55A052B;\n\tTue, 28 Jul 2020 00:05:48 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 69D081BFC8;\n\tTue, 28 Jul 2020 00:05:48 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 932672C01\n for <dev@dpdk.org>; Tue, 28 Jul 2020 00:05:47 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 06RM5kgp022466; Mon, 27 Jul 2020 15:05:47 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n by mx0b-0016f401.pphosted.com with ESMTP id 32gm8ngkjr-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 27 Jul 2020 15:05:46 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com\n (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 27 Jul 2020 15:05:44 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 27 Jul 2020 15:05:44 -0700", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n by maili.marvell.com (Postfix) with ESMTP id AA2833F7040;\n Mon, 27 Jul 2020 15:05:44 -0700 (PDT)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 06RM5i64029154;\n Mon, 27 Jul 2020 15:05:44 -0700", "(from root@localhost)\n by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 06RM5ika029145;\n Mon, 27 Jul 2020 15:05:44 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=18szoqarxB9vleElY/79QHPwBoWai+TYUUvXpIXNXMU=;\n b=VZV5heNWUkLrhVboJAbPXWUX336GocE1kN9NKXDmC0lllMsoiDWHrXsoAIYxL7ECrop0\n KHDKedE6qukNvll74B5hkT6u0tFNPIR+iNFnfFBOgkgdYpW5uvVr9QHb2FJtgbFczeH8\n mHnipERWPkjvt1YYs1MjnR+Bq5dZBmALwPbm53sZZOwyedN7hNhjnS++L7Bj5xvPs3Go\n 2k+zX6NWOk/wN2NH+6QIYqgtfQtRk96VR6Q7VfUg/UnXQTbBEkm5o9djJMW6l+OHVGA/\n mxPrKPmNSNbfZeE9AjFoj6HANpPMSOwn96bhEoG+ixaW2IrPL5fKK0rssQduS4dU7gEt Jw==", "From": "Manish Chopra <manishc@marvell.com>", "To": "<jerinjacobk@gmail.com>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>,\n <grive@u256.net>", "CC": "<dev@dpdk.org>, <irusskikh@marvell.com>, <rmody@marvell.com>,\n <GR-Everest-DPDK-Dev@marvell.com>, <rosen.xu@intel.com>,\n <tianfei.zhang@intel.com>, <heinrich.kuhn@netronome.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>", "Date": "Mon, 27 Jul 2020 15:03:39 -0700", "Message-ID": "<20200727220341.29084-5-manishc@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "In-Reply-To": "<20200727220341.29084-1-manishc@marvell.com>", "References": "<20200727220341.29084-1-manishc@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-27_15:2020-07-27,\n 2020-07-27 signatures=0", "Subject": "[dpdk-dev] [PATCH v4 4/6] net/qede: add infrastructure support for\n\tVF load", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds necessary infrastructure support (required to handle\nmessages from VF and sending ramrod on behalf of VF's configuration\nrequest from alarm handler context) to start/load the VF-PMD driver\ninstance on top of PF-PMD driver instance.\n\nSigned-off-by: Manish Chopra <manishc@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\n---\n drivers/net/qede/base/bcm_osal.c | 26 ++++++++++++\n drivers/net/qede/base/bcm_osal.h | 11 +++--\n drivers/net/qede/base/ecore.h | 4 ++\n drivers/net/qede/base/ecore_iov_api.h | 3 ++\n drivers/net/qede/qede_ethdev.c | 2 +\n drivers/net/qede/qede_main.c | 4 +-\n drivers/net/qede/qede_sriov.c | 61 +++++++++++++++++++++++++++\n drivers/net/qede/qede_sriov.h | 16 ++++++-\n 8 files changed, 121 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c\nindex 65837b53d..ef47339df 100644\n--- a/drivers/net/qede/base/bcm_osal.c\n+++ b/drivers/net/qede/base/bcm_osal.c\n@@ -14,6 +14,32 @@\n #include \"ecore_iov_api.h\"\n #include \"ecore_mcp_api.h\"\n #include \"ecore_l2_api.h\"\n+#include \"../qede_sriov.h\"\n+\n+int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn)\n+{\n+\tint rc;\n+\n+\trc = qed_schedule_iov(p_hwfn, QED_IOV_WQ_MSG_FLAG);\n+\tif (rc) {\n+\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV,\n+\t\t\t \"Failed to schedule alarm handler rc=%d\\n\", rc);\n+\t}\n+\n+\treturn rc;\n+}\n+\n+void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie)\n+{\n+\tstruct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;\n+\n+\tif (!p_hwfn)\n+\t\treturn;\n+\n+\tOSAL_SPIN_LOCK(&p_hwfn->spq_lock);\n+\tecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));\n+\tOSAL_SPIN_UNLOCK(&p_hwfn->spq_lock);\n+}\n \n /* Array of memzone pointers */\n static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];\ndiff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex 5f55cc2ee..cf58db8bf 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -178,9 +178,12 @@ typedef pthread_mutex_t osal_mutex_t;\n \n /* DPC */\n \n+void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie);\n #define OSAL_DPC_ALLOC(hwfn) OSAL_ALLOC(hwfn, GFP, sizeof(osal_dpc_t))\n-#define OSAL_DPC_INIT(dpc, hwfn) nothing\n-#define OSAL_POLL_MODE_DPC(hwfn) nothing\n+#define OSAL_DPC_INIT(dpc, hwfn) \\\n+\tOSAL_SPIN_LOCK_INIT(&(hwfn)->spq_lock)\n+#define OSAL_POLL_MODE_DPC(hwfn) \\\n+\tosal_poll_mode_dpc((osal_int_ptr_t)(p_hwfn))\n #define OSAL_DPC_SYNC(hwfn) nothing\n \n /* Lists */\n@@ -345,10 +348,12 @@ u32 qede_find_first_zero_bit(u32 *bitmap, u32 length);\n \n /* SR-IOV channel */\n \n+int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn);\n #define OSAL_VF_FLR_UPDATE(hwfn) nothing\n #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0\n #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol)\t(0)\n-#define OSAL_PF_VF_MSG(hwfn, vfid) 0\n+#define OSAL_PF_VF_MSG(hwfn, vfid) \\\n+\tosal_pf_vf_msg(hwfn)\n #define OSAL_PF_VF_MALICIOUS(hwfn, vfid) nothing\n #define OSAL_IOV_CHK_UCAST(hwfn, vfid, params) 0\n #define OSAL_IOV_POST_START_VPORT(hwfn, vf, vport_id, opaque_fid) nothing\ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex 750e99a8f..6c8e6d407 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -714,6 +714,10 @@ struct ecore_hwfn {\n \n \t/* @DPDK */\n \tstruct ecore_ptt\t\t*p_arfs_ptt;\n+\n+\t/* DPDK specific, not the part of vanilla ecore */\n+\tosal_spinlock_t spq_lock;\n+\tu32 iov_task_flags;\n };\n \n enum ecore_mf_mode {\ndiff --git a/drivers/net/qede/base/ecore_iov_api.h b/drivers/net/qede/base/ecore_iov_api.h\nindex 545001812..bd7c5703f 100644\n--- a/drivers/net/qede/base/ecore_iov_api.h\n+++ b/drivers/net/qede/base/ecore_iov_api.h\n@@ -14,6 +14,9 @@\n #define ECORE_ETH_VF_NUM_VLAN_FILTERS 2\n #define ECORE_VF_ARRAY_LENGTH (3)\n \n+#define ECORE_VF_ARRAY_GET_VFID(arr, vfid)\t\\\n+\t(((arr)[(vfid) / 64]) & (1ULL << ((vfid) % 64)))\n+\n #define IS_VF(p_dev)\t\t((p_dev)->b_is_vf)\n #define IS_PF(p_dev)\t\t(!((p_dev)->b_is_vf))\n #ifdef CONFIG_ECORE_SRIOV\ndiff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c\nindex 0235c0798..210a3b10f 100644\n--- a/drivers/net/qede/qede_ethdev.c\n+++ b/drivers/net/qede/qede_ethdev.c\n@@ -281,7 +281,9 @@ qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)\n \n static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)\n {\n+\tOSAL_SPIN_LOCK(&p_hwfn->spq_lock);\n \tecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));\n+\tOSAL_SPIN_UNLOCK(&p_hwfn->spq_lock);\n }\n \n static void\ndiff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c\nindex c37e8ebe0..0afacc064 100644\n--- a/drivers/net/qede/qede_main.c\n+++ b/drivers/net/qede/qede_main.c\n@@ -221,7 +221,9 @@ static void qed_stop_iov_task(struct ecore_dev *edev)\n \n \tfor_each_hwfn(edev, i) {\n \t\tp_hwfn = &edev->hwfns[i];\n-\t\tif (!IS_PF(edev))\n+\t\tif (IS_PF(edev))\n+\t\t\trte_eal_alarm_cancel(qed_iov_pf_task, p_hwfn);\n+\t\telse\n \t\t\trte_eal_alarm_cancel(qede_vf_task, p_hwfn);\n \t}\n }\ndiff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c\nindex ba4384e90..6d620dde8 100644\n--- a/drivers/net/qede/qede_sriov.c\n+++ b/drivers/net/qede/qede_sriov.c\n@@ -4,6 +4,14 @@\n * www.marvell.com\n */\n \n+#include <rte_alarm.h>\n+\n+#include \"base/bcm_osal.h\"\n+#include \"base/ecore.h\"\n+#include \"base/ecore_sriov.h\"\n+#include \"base/ecore_mcp.h\"\n+#include \"base/ecore_vf.h\"\n+\n #include \"qede_sriov.h\"\n \n static void qed_sriov_enable_qid_config(struct ecore_hwfn *hwfn,\n@@ -83,3 +91,56 @@ void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param)\n \tif (num_vfs_param)\n \t\tqed_sriov_enable(edev, num_vfs_param);\n }\n+\n+static void qed_handle_vf_msg(struct ecore_hwfn *hwfn)\n+{\n+\tu64 events[ECORE_VF_ARRAY_LENGTH];\n+\tstruct ecore_ptt *ptt;\n+\tint i;\n+\n+\tptt = ecore_ptt_acquire(hwfn);\n+\tif (!ptt) {\n+\t\tDP_NOTICE(hwfn, true, \"PTT acquire failed\\n\");\n+\t\tqed_schedule_iov(hwfn, QED_IOV_WQ_MSG_FLAG);\n+\t\treturn;\n+\t}\n+\n+\tecore_iov_pf_get_pending_events(hwfn, events);\n+\n+\tecore_for_each_vf(hwfn, i) {\n+\t\t/* Skip VFs with no pending messages */\n+\t\tif (!ECORE_VF_ARRAY_GET_VFID(events, i))\n+\t\t\tcontinue;\n+\n+\t\tDP_VERBOSE(hwfn, ECORE_MSG_IOV,\n+\t\t\t \"Handling VF message from VF 0x%02x [Abs 0x%02x]\\n\",\n+\t\t\t i, hwfn->p_dev->p_iov_info->first_vf_in_pf + i);\n+\n+\t\t/* Copy VF's message to PF's request buffer for that VF */\n+\t\tif (ecore_iov_copy_vf_msg(hwfn, ptt, i))\n+\t\t\tcontinue;\n+\n+\t\tecore_iov_process_mbx_req(hwfn, ptt, i);\n+\t}\n+\n+\tecore_ptt_release(hwfn, ptt);\n+}\n+\n+void qed_iov_pf_task(void *arg)\n+{\n+\tstruct ecore_hwfn *p_hwfn = arg;\n+\n+\tif (OSAL_GET_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags)) {\n+\t\tOSAL_CLEAR_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags);\n+\t\tqed_handle_vf_msg(p_hwfn);\n+\t}\n+}\n+\n+int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag)\n+{\n+\tDP_VERBOSE(p_hwfn, ECORE_MSG_IOV, \"Scheduling iov task [Flag: %d]\\n\",\n+\t\t flag);\n+\n+\tOSAL_SET_BIT(flag, &p_hwfn->iov_task_flags);\n+\treturn rte_eal_alarm_set(1, qed_iov_pf_task, p_hwfn);\n+}\ndiff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h\nindex 6c85b1dd5..8b7fa7daa 100644\n--- a/drivers/net/qede/qede_sriov.h\n+++ b/drivers/net/qede/qede_sriov.h\n@@ -4,6 +4,18 @@\n * www.marvell.com\n */\n \n-#include \"qede_ethdev.h\"\n-\n void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param);\n+\n+enum qed_iov_wq_flag {\n+\tQED_IOV_WQ_MSG_FLAG,\n+\tQED_IOV_WQ_SET_UNICAST_FILTER_FLAG,\n+\tQED_IOV_WQ_BULLETIN_UPDATE_FLAG,\n+\tQED_IOV_WQ_STOP_WQ_FLAG,\n+\tQED_IOV_WQ_FLR_FLAG,\n+\tQED_IOV_WQ_TRUST_FLAG,\n+\tQED_IOV_WQ_VF_FORCE_LINK_QUERY_FLAG,\n+\tQED_IOV_WQ_DB_REC_HANDLER,\n+};\n+\n+int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag);\n+void qed_iov_pf_task(void *arg);\n", "prefixes": [ "v4", "4/6" ] }