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{
    "id": 74337,
    "url": "http://patches.dpdk.org/api/patches/74337/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594982985-31551-4-git-send-email-radu.nicolau@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1594982985-31551-4-git-send-email-radu.nicolau@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1594982985-31551-4-git-send-email-radu.nicolau@intel.com",
    "date": "2020-07-17T10:49:44",
    "name": "[v8,3/4] common/qat: use WC store to update queue tail registers",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "717aff0e3537cd12ee766de014e1bcac4f2bbe03",
    "submitter": {
        "id": 743,
        "url": "http://patches.dpdk.org/api/people/743/?format=api",
        "name": "Radu Nicolau",
        "email": "radu.nicolau@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594982985-31551-4-git-send-email-radu.nicolau@intel.com/mbox/",
    "series": [
        {
            "id": 11126,
            "url": "http://patches.dpdk.org/api/series/11126/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11126",
            "date": "2020-07-17T10:49:41",
            "name": "eal: add WC store functions",
            "version": 8,
            "mbox": "http://patches.dpdk.org/series/11126/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/74337/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/74337/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8E6F8A053D;\n\tFri, 17 Jul 2020 12:50:42 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C1DFA1C066;\n\tFri, 17 Jul 2020 12:50:21 +0200 (CEST)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by dpdk.org (Postfix) with ESMTP id BFDB51C02D\n for <dev@dpdk.org>; Fri, 17 Jul 2020 12:50:19 +0200 (CEST)",
            "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Jul 2020 03:50:19 -0700",
            "from silpixa00383879.ir.intel.com ([10.237.222.142])\n by fmsmga004.fm.intel.com with ESMTP; 17 Jul 2020 03:50:17 -0700"
        ],
        "IronPort-SDR": [
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            "\n 24c3f/LJOz/Ye9XFYxEiiS0zwYt1EMohDgNzgfRYuP/SOTnSEaiSKw47vgzNq59oWCIRDCiH0V\n qdcbi4JHMi8Q=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9684\"; a=\"129131828\"",
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            "E=Sophos;i=\"5.75,362,1589266800\"; d=\"scan'208\";a=\"308983651\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Radu Nicolau <radu.nicolau@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "beilei.xing@intel.com, jia.guo@intel.com, bruce.richardson@intel.com,\n konstantin.ananyev@intel.com, jerinjacobk@gmail.com,\n david.marchand@redhat.com, fiona.trahe@intel.com, wei.zhao1@intel.com,\n ruifeng.wang@arm.com, Radu Nicolau <radu.nicolau@intel.com>",
        "Date": "Fri, 17 Jul 2020 11:49:44 +0100",
        "Message-Id": "<1594982985-31551-4-git-send-email-radu.nicolau@intel.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1594982985-31551-1-git-send-email-radu.nicolau@intel.com>",
        "References": "<1591870283-7776-1-git-send-email-radu.nicolau@intel.com>\n <1594982985-31551-1-git-send-email-radu.nicolau@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v8 3/4] common/qat: use WC store to update queue\n\ttail registers",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Performance improvement: use a write combining store\ninstead of a regular mmio write to update queue tail\nregisters.\n\nSigned-off-by: Radu Nicolau <radu.nicolau@intel.com>\n---\n drivers/common/qat/qat_adf/adf_transport_access_macros.h | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros.h b/drivers/common/qat/qat_adf/adf_transport_access_macros.h\nindex 1eef551..504ffb7 100644\n--- a/drivers/common/qat/qat_adf/adf_transport_access_macros.h\n+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros.h\n@@ -9,6 +9,8 @@\n /* CSR write macro */\n #define ADF_CSR_WR(csrAddr, csrOffset, val)\t\t\\\n \trte_write32(val, (((uint8_t *)csrAddr) + csrOffset))\n+#define ADF_CSR_WC_WR(csrAddr, csrOffset, val)\t\t\\\n+\trte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset))\n \n /* CSR read macro */\n #define ADF_CSR_RD(csrAddr, csrOffset)\t\t\t\\\n@@ -110,10 +112,10 @@ do { \\\n \t\tADF_RING_CSR_RING_UBASE + (ring << 2), u_base);\t\\\n } while (0)\n #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \\\n-\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\tADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n \t\tADF_RING_CSR_RING_HEAD + (ring << 2), value)\n #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \\\n-\tADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n+\tADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \\\n \t\tADF_RING_CSR_RING_TAIL + (ring << 2), value)\n #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \\\n do { \\\n",
    "prefixes": [
        "v8",
        "3/4"
    ]
}