Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/74158/?format=api
{ "id": 74158, "url": "http://patches.dpdk.org/api/patches/74158/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594875225-5850-2-git-send-email-phil.yang@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594875225-5850-2-git-send-email-phil.yang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594875225-5850-2-git-send-email-phil.yang@arm.com", "date": "2020-07-16T04:53:42", "name": "[v8,1/3] doc: add optimizations using C11 atomic built-ins", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "36e469e85da86b4e9537c738695bf4bb38fe5cb7", "submitter": { "id": 833, "url": "http://patches.dpdk.org/api/people/833/?format=api", "name": "Phil Yang", "email": "phil.yang@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594875225-5850-2-git-send-email-phil.yang@arm.com/mbox/", "series": [ { "id": 11068, "url": "http://patches.dpdk.org/api/series/11068/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11068", "date": "2020-07-16T04:53:41", "name": "generic rte atomic APIs deprecate proposal", "version": 8, "mbox": "http://patches.dpdk.org/series/11068/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74158/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/74158/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0C6A0A0540;\n\tThu, 16 Jul 2020 06:58:18 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D8C941BEA8;\n\tThu, 16 Jul 2020 06:58:07 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 3B1944F9A\n for <dev@dpdk.org>; Thu, 16 Jul 2020 06:58:06 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BDA3731B;\n Wed, 15 Jul 2020 21:58:05 -0700 (PDT)", "from phil-VirtualBox.shanghai.arm.com\n (phil-VirtualBox.shanghai.arm.com [10.169.109.137])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 866CB3F66B;\n Wed, 15 Jul 2020 21:58:01 -0700 (PDT)" ], "From": "Phil Yang <phil.yang@arm.com>", "To": "thomas@monjalon.net, john.mcnamara@intel.com,\n Honnappa.Nagarahalli@arm.com,\n drc@linux.vnet.ibm.com, dev@dpdk.org", "Cc": "david.marchand@redhat.com, jerinj@marvell.com,\n konstantin.ananyev@intel.com, Ola.Liljedahl@arm.com,\n bruce.richardson@intel.com, Ruifeng.Wang@arm.com, nd@arm.com,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,\n Marko Kovacevic <marko.kovacevic@intel.com>", "Date": "Thu, 16 Jul 2020 12:53:42 +0800", "Message-Id": "<1594875225-5850-2-git-send-email-phil.yang@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1594875225-5850-1-git-send-email-phil.yang@arm.com>", "References": "<1594621423-14796-1-git-send-email-phil.yang@arm.com>\n <1594875225-5850-1-git-send-email-phil.yang@arm.com>", "Subject": "[dpdk-dev] [PATCH v8 1/3] doc: add optimizations using C11 atomic\n\tbuilt-ins", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add information about possible optimizations using C11 atomic built-ins.\n\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nSigned-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\n---\n doc/guides/prog_guide/writing_efficient_code.rst | 59 +++++++++++++++++++++++-\n 1 file changed, 58 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/prog_guide/writing_efficient_code.rst b/doc/guides/prog_guide/writing_efficient_code.rst\nindex 849f63e..53a1ca1 100644\n--- a/doc/guides/prog_guide/writing_efficient_code.rst\n+++ b/doc/guides/prog_guide/writing_efficient_code.rst\n@@ -167,7 +167,13 @@ but with the added cost of lower throughput.\n Locks and Atomic Operations\n ---------------------------\n \n-Atomic operations imply a lock prefix before the instruction,\n+This section describes some key considerations when using locks and atomic\n+operations in the DPDK environment.\n+\n+Locks\n+~~~~~\n+\n+On x86, atomic operations imply a lock prefix before the instruction,\n causing the processor's LOCK# signal to be asserted during execution of the following instruction.\n This has a big impact on performance in a multicore environment.\n \n@@ -176,6 +182,57 @@ It can often be replaced by other solutions like per-lcore variables.\n Also, some locking techniques are more efficient than others.\n For instance, the Read-Copy-Update (RCU) algorithm can frequently replace simple rwlocks.\n \n+Atomic Operations: Use C11 Atomic Built-ins\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+DPDK generic rte_atomic operations are implemented by __sync built-ins. These\n+__sync built-ins result in full barriers on aarch64, which are unnecessary\n+in many use cases. They can be replaced by __atomic built-ins that conform to\n+the C11 memory model and provide finer memory order control.\n+\n+So replacing the rte_atomic operations with __atomic built-ins might improve\n+performance for aarch64 machines.\n+\n+Some typical optimization cases are listed below:\n+\n+Atomicity\n+^^^^^^^^^\n+\n+Some use cases require atomicity alone, the ordering of the memory operations\n+does not matter. For example, the packet statistics counters need to be\n+incremented atomically but do not need any particular memory ordering.\n+So, RELAXED memory ordering is sufficient.\n+\n+One-way Barrier\n+^^^^^^^^^^^^^^^\n+\n+Some use cases allow for memory reordering in one way while requiring memory\n+ordering in the other direction.\n+\n+For example, the memory operations before the spinlock lock are allowed to\n+move to the critical section, but the memory operations in the critical section\n+are not allowed to move above the lock. In this case, the full memory barrier\n+in the compare-and-swap operation can be replaced with ACQUIRE memory order.\n+On the other hand, the memory operations after the spinlock unlock are allowed\n+to move to the critical section, but the memory operations in the critical\n+section are not allowed to move below the unlock. So the full barrier in the\n+store operation can use RELEASE memory order.\n+\n+Reader-Writer Concurrency\n+^^^^^^^^^^^^^^^^^^^^^^^^^\n+\n+Lock-free reader-writer concurrency is one of the common use cases in DPDK.\n+\n+The payload or the data that the writer wants to communicate to the reader,\n+can be written with RELAXED memory order. However, the guard variable should\n+be written with RELEASE memory order. This ensures that the store to guard\n+variable is observable only after the store to payload is observable.\n+\n+Correspondingly, on the reader side, the guard variable should be read\n+with ACQUIRE memory order. The payload or the data the writer communicated,\n+can be read with RELAXED memory order. This ensures that, if the store to\n+guard variable is observable, the store to payload is also observable.\n+\n Coding Considerations\n ---------------------\n \n", "prefixes": [ "v8", "1/3" ] }