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GET /api/patches/74051/?format=api
{ "id": 74051, "url": "http://patches.dpdk.org/api/patches/74051/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-9-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1594794114-16313-9-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1594794114-16313-9-git-send-email-viacheslavo@mellanox.com", "date": "2020-07-15T06:21:45", "name": "[v2,08/17] net/mlx5: allocate packet pacing context", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "58efa2757e0860dd93a7a7b08d45d6eb8eba9c16", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1594794114-16313-9-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 11032, "url": "http://patches.dpdk.org/api/series/11032/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11032", "date": "2020-07-15T06:21:37", "name": "net/mlx5: introduce accurate packet Tx scheduling", "version": 2, "mbox": "http://patches.dpdk.org/series/11032/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/74051/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/74051/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9A74EA0540;\n\tWed, 15 Jul 2020 08:23:40 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 738801C19A;\n\tWed, 15 Jul 2020 08:22:24 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 8C9CE1C0B2\n for <dev@dpdk.org>; Wed, 15 Jul 2020 08:22:17 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com) with SMTP; 15 Jul 2020 09:22:12 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n [10.210.17.40])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06F6MCp7007043;\n Wed, 15 Jul 2020 09:22:12 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06F6MCVv016442;\n Wed, 15 Jul 2020 06:22:12 GMT", "(from viacheslavo@localhost)\n by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06F6MC94016441;\n Wed, 15 Jul 2020 06:22:12 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, olivier.matz@6wind.com,\n thomas@monjalon.net, ferruh.yigit@intel.com", "Date": "Wed, 15 Jul 2020 06:21:45 +0000", "Message-Id": "<1594794114-16313-9-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1591771085-24959-1-git-send-email-viacheslavo@mellanox.com>\n <1594794114-16313-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 08/17] net/mlx5: allocate packet pacing context", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch allocates the Packet Pacing context from the kernel,\nconfigures one according to requested pace send scheduling\ngranularuty and assigns to Clock Queue.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.h | 2 ++\n drivers/net/mlx5/mlx5_txpp.c | 71 ++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 73 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 61a93f9..e8a7b10 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -568,6 +568,8 @@ struct mlx5_dev_txpp {\n \tstruct mlx5dv_devx_event_channel *echan; /* Event Channel. */\n \tstruct mlx5_txpp_wq clock_queue; /* Clock Queue. */\n \tstruct mlx5_txpp_wq rearm_queue; /* Clock Queue. */\n+\tstruct mlx5dv_pp *pp; /* Packet pacing context. */\n+\tuint16_t pp_id; /* Packet pacing context index. */\n };\n \n /*\ndiff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c\nindex f600fc5..a0ee872 100644\n--- a/drivers/net/mlx5/mlx5_txpp.c\n+++ b/drivers/net/mlx5/mlx5_txpp.c\n@@ -6,6 +6,7 @@\n #include <rte_interrupts.h>\n #include <rte_alarm.h>\n #include <rte_malloc.h>\n+#include <rte_cycles.h>\n \n #include \"mlx5.h\"\n #include \"mlx5_rxtx.h\"\n@@ -49,6 +50,69 @@\n }\n \n static void\n+mlx5_txpp_free_pp_index(struct mlx5_dev_ctx_shared *sh)\n+{\n+\tif (sh->txpp.pp) {\n+\t\tmlx5_glue->dv_free_pp(sh->txpp.pp);\n+\t\tsh->txpp.pp = NULL;\n+\t\tsh->txpp.pp_id = 0;\n+\t}\n+}\n+\n+/* Allocate Packet Pacing index from kernel via mlx5dv call. */\n+static int\n+mlx5_txpp_alloc_pp_index(struct mlx5_dev_ctx_shared *sh)\n+{\n+#ifdef HAVE_MLX5DV_PP_ALLOC\n+\tuint32_t pp[MLX5_ST_SZ_DW(set_pp_rate_limit_context)];\n+\tuint64_t rate;\n+\n+\tMLX5_ASSERT(!sh->txpp.pp);\n+\tmemset(&pp, 0, sizeof(pp));\n+\trate = NS_PER_S / sh->txpp.tick;\n+\tif (rate * sh->txpp.tick != NS_PER_S)\n+\t\tDRV_LOG(WARNING, \"Packet pacing frequency is not precise.\");\n+\tif (sh->txpp.test) {\n+\t\tuint32_t len;\n+\n+\t\tlen = RTE_MAX(MLX5_TXPP_TEST_PKT_SIZE,\n+\t\t\t (size_t)RTE_ETHER_MIN_LEN);\n+\t\tMLX5_SET(set_pp_rate_limit_context, &pp,\n+\t\t\t burst_upper_bound, len);\n+\t\tMLX5_SET(set_pp_rate_limit_context, &pp,\n+\t\t\t typical_packet_size, len);\n+\t\t/* Convert packets per second into kilobits. */\n+\t\trate = (rate * len) / (1000ul / CHAR_BIT);\n+\t\tDRV_LOG(INFO, \"Packet pacing rate set to %\" PRIu64, rate);\n+\t}\n+\tMLX5_SET(set_pp_rate_limit_context, &pp, rate_limit, rate);\n+\tMLX5_SET(set_pp_rate_limit_context, &pp, rate_mode,\n+\t\t sh->txpp.test ? MLX5_DATA_RATE : MLX5_WQE_RATE);\n+\tsh->txpp.pp = mlx5_glue->dv_alloc_pp\n+\t\t\t\t(sh->ctx, sizeof(pp), &pp,\n+\t\t\t\t MLX5DV_PP_ALLOC_FLAGS_DEDICATED_INDEX);\n+\tif (sh->txpp.pp == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate packet pacing index.\");\n+\t\trte_errno = errno;\n+\t\treturn -errno;\n+\t}\n+\tif (!sh->txpp.pp->index) {\n+\t\tDRV_LOG(ERR, \"Zero packet pacing index allocated.\");\n+\t\tmlx5_txpp_free_pp_index(sh);\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -ENOTSUP;\n+\t}\n+\tsh->txpp.pp_id = sh->txpp.pp->index;\n+\treturn 0;\n+#else\n+\tRTE_SET_USED(sh);\n+\tDRV_LOG(ERR, \"Allocating pacing index is not supported.\");\n+\trte_errno = ENOTSUP;\n+\treturn -ENOTSUP;\n+#endif\n+}\n+\n+static void\n mlx5_txpp_destroy_send_queue(struct mlx5_txpp_wq *wq)\n {\n \tif (wq->sq)\n@@ -457,6 +521,7 @@\n \t}\n \tsq_attr.state = MLX5_SQC_STATE_RST;\n \tsq_attr.cqn = wq->cq->id;\n+\tsq_attr.packet_pacing_rate_limit_index = sh->txpp.pp_id;\n \tsq_attr.wq_attr.cd_slave = 1;\n \tsq_attr.wq_attr.uar_page = sh->tx_uar->page_id;\n \tsq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;\n@@ -503,6 +568,7 @@\n * - Clock CQ/SQ\n * - Rearm CQ/SQ\n * - attaches rearm interrupt handler\n+ * - starts Clock Queue\n *\n * Returns 0 on success, negative otherwise\n */\n@@ -520,6 +586,9 @@\n \tret = mlx5_txpp_create_eqn(sh);\n \tif (ret)\n \t\tgoto exit;\n+\tret = mlx5_txpp_alloc_pp_index(sh);\n+\tif (ret)\n+\t\tgoto exit;\n \tret = mlx5_txpp_create_clock_queue(sh);\n \tif (ret)\n \t\tgoto exit;\n@@ -530,6 +599,7 @@\n \tif (ret) {\n \t\tmlx5_txpp_destroy_rearm_queue(sh);\n \t\tmlx5_txpp_destroy_clock_queue(sh);\n+\t\tmlx5_txpp_free_pp_index(sh);\n \t\tmlx5_txpp_destroy_eqn(sh);\n \t\tsh->txpp.tick = 0;\n \t\tsh->txpp.test = 0;\n@@ -550,6 +620,7 @@\n {\n \tmlx5_txpp_destroy_rearm_queue(sh);\n \tmlx5_txpp_destroy_clock_queue(sh);\n+\tmlx5_txpp_free_pp_index(sh);\n \tmlx5_txpp_destroy_eqn(sh);\n \tsh->txpp.tick = 0;\n \tsh->txpp.test = 0;\n", "prefixes": [ "v2", "08/17" ] }