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GET /api/patches/73960/?format=api
{ "id": 73960, "url": "http://patches.dpdk.org/api/patches/73960/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200713151319.17547-4-manishc@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200713151319.17547-4-manishc@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200713151319.17547-4-manishc@marvell.com", "date": "2020-07-13T15:13:15", "name": "[v2,3/7] net/qede: define PCI config space specific osals", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "119be4044eb64dedddedafe83ecf615c33bb0e70", "submitter": { "id": 1591, "url": "http://patches.dpdk.org/api/people/1591/?format=api", "name": "Manish Chopra", "email": "manishc@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200713151319.17547-4-manishc@marvell.com/mbox/", "series": [ { "id": 11003, "url": "http://patches.dpdk.org/api/series/11003/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=11003", "date": "2020-07-13T15:13:12", "name": "qede: SR-IOV PF driver support", "version": 2, "mbox": "http://patches.dpdk.org/series/11003/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/73960/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/73960/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3EB78A0540;\n\tMon, 13 Jul 2020 17:15:15 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 21C6C1D61E;\n\tMon, 13 Jul 2020 17:15:15 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 086891D615\n for <dev@dpdk.org>; Mon, 13 Jul 2020 17:15:13 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 06DFARIJ004295; Mon, 13 Jul 2020 08:15:08 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n by mx0a-0016f401.pphosted.com with ESMTP id 327asn7ypc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 13 Jul 2020 08:15:08 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com\n (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 13 Jul 2020 08:15:07 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 13 Jul 2020 08:15:07 -0700", "from dut1171.mv.qlogic.com (unknown [10.112.88.18])\n by maili.marvell.com (Postfix) with ESMTP id 548F13F7044;\n Mon, 13 Jul 2020 08:15:07 -0700 (PDT)", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\n by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 06DFF7ue017613;\n Mon, 13 Jul 2020 08:15:07 -0700", "(from root@localhost)\n by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 06DFF7Cw017612;\n Mon, 13 Jul 2020 08:15:07 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=hkDA7pHGOGSWyIq+M6csNxdodXGyXA+5tbDRtuBv2+0=;\n b=sg1l5kbVFze0VWcpnyFL+FTVmWUtWsiqxNdqLLI+tGNqr2uxgI6DtRP0BNOfDnOrmaMb\n 3TL3gOlNJaYbUrFEcF/aIyPYDiPcf+OEW+INquYF0pem6kgPJMKscHvg4o5uVcQWlmvM\n iZgdZTtPUy3jK53WuX+4dRHJD1Ft5dAy/1tpRfdFXeaFTSD4bLe6VgE+huOyfv1sDwFc\n k6W00TJ4gSyYrURixRGWknL+MUGd6psmW14ismvg37ztzyWOQhwQ7pjIeaJ9Wz1s2Ugy\n IfTS1QwHqZu/34aixioW4hx2erAEQ5t6RxL1lNCeoCRkhxWpGQejagXOofSSmO3hYhtG KA==", "From": "Manish Chopra <manishc@marvell.com>", "To": "<jerinjacobk@gmail.com>, <jerinj@marvell.com>, <ferruh.yigit@intel.com>,\n <grive@u256.net>", "CC": "<dev@dpdk.org>, <irusskikh@marvell.com>, <rmody@marvell.com>,\n <GR-Everest-DPDK-Dev@marvell.com>, <anatoly.burakov@intel.com>,\n <xavier.huwei@huawei.com>, <humin29@huawei.com>,\n <yisen.zhuang@huawei.com>, <xiao.w.wang@intel.com>,\n <qiming.yang@intel.com>, <qi.z.zhang@intel.com>,\n <heinrich.kuhn@netronome.com>", "Date": "Mon, 13 Jul 2020 08:13:15 -0700", "Message-ID": "<20200713151319.17547-4-manishc@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "In-Reply-To": "<20200713151319.17547-1-manishc@marvell.com>", "References": "<20200713151319.17547-1-manishc@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-07-13_14:2020-07-13,\n 2020-07-13 signatures=0", "Subject": "[dpdk-dev] [PATCH v2 3/7] net/qede: define PCI config space\n\tspecific osals", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch defines various PCI config space access APIs\nin order to read and find IOV specific PCI capabilities.\n\nWith these definitions implemented, it enables the base\ndriver to do SR-IOV specific initialization and HW specific\nconfiguration required from PF-PMD driver instance.\n\nSigned-off-by: Manish Chopra <manishc@marvell.com>\nSigned-off-by: Igor Russkikh <irusskikh@marvell.com>\nSigned-off-by: Rasesh Mody <rmody@marvell.com>\n---\n drivers/net/qede/base/bcm_osal.h | 18 +++++++++++++-----\n drivers/net/qede/base/ecore.h | 3 +++\n drivers/net/qede/qede_main.c | 1 +\n 3 files changed, 17 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h\nindex 5d4df5907..317e088e1 100644\n--- a/drivers/net/qede/base/bcm_osal.h\n+++ b/drivers/net/qede/base/bcm_osal.h\n@@ -21,6 +21,11 @@\n #include <rte_ether.h>\n #include <rte_io.h>\n #include <rte_version.h>\n+#include <rte_bus_pci.h>\n+#include <rte_pci_regs.h>\n+\n+#define PCICFG_VENDOR_ID_OFFSET PCI_VENDOR_ID\n+#define PCICFG_DEVICE_ID_OFFSET PCI_DEVICE_ID\n \n /* Forward declaration */\n struct ecore_dev;\n@@ -286,11 +291,14 @@ typedef struct osal_list_t {\n \tOSAL_LIST_PUSH_HEAD(new_entry, list)\n \n /* PCI config space */\n-\n-#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) nothing\n-#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) nothing\n-#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) nothing\n-#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, pcie_id) 0\n+#define OSAL_PCI_READ_CONFIG_BYTE(dev, address, dst) \\\n+\trte_pci_read_config((dev)->pci_dev, dst, 1, address)\n+#define OSAL_PCI_READ_CONFIG_WORD(dev, address, dst) \\\n+\trte_pci_read_config((dev)->pci_dev, dst, 2, address)\n+#define OSAL_PCI_READ_CONFIG_DWORD(dev, address, dst) \\\n+\trte_pci_read_config((dev)->pci_dev, dst, 4, address)\n+#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, cap) \\\n+\trte_pci_find_next_ext_capability((dev)->pci_dev, cap)\n #define OSAL_PCI_FIND_CAPABILITY(dev, pcie_id) 0\n #define OSAL_PCI_WRITE_CONFIG_WORD(dev, address, val) nothing\n #define OSAL_BAR_SIZE(dev, bar_id) 0\ndiff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex 63bd7466a..750e99a8f 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -937,6 +937,9 @@ struct ecore_dev {\n \tstruct ecore_dbg_feature\tdbg_features[DBG_FEATURE_NUM];\n \tstruct ecore_dbg_params\t\tdbg_params;\n \tosal_mutex_t\t\t\tdbg_lock;\n+\n+\t/* DPDK specific ecore field */\n+\tstruct rte_pci_device\t\t*pci_dev;\n };\n \n enum ecore_hsi_def_type {\ndiff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c\nindex 987a6f1e1..d919f9f11 100644\n--- a/drivers/net/qede/qede_main.c\n+++ b/drivers/net/qede/qede_main.c\n@@ -37,6 +37,7 @@ static void qed_init_pci(struct ecore_dev *edev, struct rte_pci_device *pci_dev)\n \tedev->regview = pci_dev->mem_resource[0].addr;\n \tedev->doorbells = pci_dev->mem_resource[2].addr;\n \tedev->db_size = pci_dev->mem_resource[2].len;\n+\tedev->pci_dev = pci_dev;\n }\n \n static int\n", "prefixes": [ "v2", "3/7" ] }