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GET /api/patches/73925/?format=api
{ "id": 73925, "url": "http://patches.dpdk.org/api/patches/73925/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/5f21383ad8be73690f5104682ac0afac2ff7df9a.1594640823.git.vladimir.medvedkin@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<5f21383ad8be73690f5104682ac0afac2ff7df9a.1594640823.git.vladimir.medvedkin@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/5f21383ad8be73690f5104682ac0afac2ff7df9a.1594640823.git.vladimir.medvedkin@intel.com", "date": "2020-07-13T11:56:28", "name": "[v7,4/8] fib: introduce AVX512 lookup", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3b499496268bb992046102b9c83ca7912b71c6c9", "submitter": { "id": 1216, "url": "http://patches.dpdk.org/api/people/1216/?format=api", "name": "Vladimir Medvedkin", "email": "vladimir.medvedkin@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/5f21383ad8be73690f5104682ac0afac2ff7df9a.1594640823.git.vladimir.medvedkin@intel.com/mbox/", "series": [ { "id": 10990, "url": "http://patches.dpdk.org/api/series/10990/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10990", "date": "2020-07-13T11:56:24", "name": "fib: implement AVX512 vector lookup", "version": 7, "mbox": "http://patches.dpdk.org/series/10990/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/73925/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/73925/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B0840A0540;\n\tMon, 13 Jul 2020 13:57:08 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 545E91D683;\n\tMon, 13 Jul 2020 13:56:48 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n by dpdk.org (Postfix) with ESMTP id 841031D676\n for <dev@dpdk.org>; Mon, 13 Jul 2020 13:56:44 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Jul 2020 04:56:44 -0700", "from silpixa00400322.ir.intel.com ([10.237.214.86])\n by orsmga004.jf.intel.com with ESMTP; 13 Jul 2020 04:56:41 -0700" ], "IronPort-SDR": [ "\n R8lWz932QKVpeUhUN1QMmO/aP/TmNQhPtAnaTbMR/U/kvsjBmLEtrlTUYK/prNY0hs1wuMOvUm\n 6+4N43O4DMDQ==", "\n il71um1LrpTMDGZwVDZ9a1Rjw7K8di35gt1iMxNeRJ3vGrm9hkDxO3uUZIaAgFTGHQvBwd/kHc\n dme9+jg/zh3A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9680\"; a=\"233454705\"", "E=Sophos;i=\"5.75,347,1589266800\"; d=\"scan'208\";a=\"233454705\"", "E=Sophos;i=\"5.75,347,1589266800\"; d=\"scan'208\";a=\"429360225\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Vladimir Medvedkin <vladimir.medvedkin@intel.com>", "To": "dev@dpdk.org", "Cc": "david.marchand@redhat.com, jerinj@marvell.com, mdr@ashroe.eu,\n thomas@monjalon.net, konstantin.ananyev@intel.com,\n bruce.richardson@intel.com", "Date": "Mon, 13 Jul 2020 12:56:28 +0100", "Message-Id": "\n <5f21383ad8be73690f5104682ac0afac2ff7df9a.1594640823.git.vladimir.medvedkin@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": [ "<cover.1594640822.git.vladimir.medvedkin@intel.com>", "<cover.1594640822.git.vladimir.medvedkin@intel.com>" ], "References": [ "<cover.1594640822.git.vladimir.medvedkin@intel.com>", "<cover.1594638050.git.vladimir.medvedkin@intel.com>\n <cover.1594640822.git.vladimir.medvedkin@intel.com>" ], "Subject": "[dpdk-dev] [PATCH v7 4/8] fib: introduce AVX512 lookup", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add new lookup implementation for DIR24_8 algorithm using\nAVX512 instruction set\n\nSigned-off-by: Vladimir Medvedkin <vladimir.medvedkin@intel.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n lib/librte_fib/Makefile | 14 +++\n lib/librte_fib/dir24_8.c | 24 +++++\n lib/librte_fib/dir24_8_avx512.c | 165 ++++++++++++++++++++++++++++++++\n lib/librte_fib/dir24_8_avx512.h | 24 +++++\n lib/librte_fib/meson.build | 18 ++++\n lib/librte_fib/rte_fib.h | 3 +-\n 6 files changed, 247 insertions(+), 1 deletion(-)\n create mode 100644 lib/librte_fib/dir24_8_avx512.c\n create mode 100644 lib/librte_fib/dir24_8_avx512.h", "diff": "diff --git a/lib/librte_fib/Makefile b/lib/librte_fib/Makefile\nindex 1dd2a495b..3958da106 100644\n--- a/lib/librte_fib/Makefile\n+++ b/lib/librte_fib/Makefile\n@@ -19,4 +19,18 @@ SRCS-$(CONFIG_RTE_LIBRTE_FIB) := rte_fib.c rte_fib6.c dir24_8.c trie.c\n # install this header file\n SYMLINK-$(CONFIG_RTE_LIBRTE_FIB)-include := rte_fib.h rte_fib6.h\n \n+CC_AVX512F_SUPPORT=$(shell $(CC) -mavx512f -dM -E - </dev/null 2>&1 | \\\n+grep -q __AVX512F__ && echo 1)\n+\n+CC_AVX512DQ_SUPPORT=$(shell $(CC) -mavx512dq -dM -E - </dev/null 2>&1 | \\\n+grep -q __AVX512DQ__ && echo 1)\n+\n+ifeq ($(CC_AVX512F_SUPPORT), 1)\n+\tifeq ($(CC_AVX512DQ_SUPPORT), 1)\n+\t\tSRCS-$(CONFIG_RTE_LIBRTE_FIB) += dir24_8_avx512.c\n+\t\tCFLAGS_dir24_8_avx512.o += -mavx512f\n+\t\tCFLAGS_dir24_8_avx512.o += -mavx512dq\n+\t\tCFLAGS_dir24_8.o += -DCC_DIR24_8_AVX512_SUPPORT\n+\tendif\n+endif\n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/lib/librte_fib/dir24_8.c b/lib/librte_fib/dir24_8.c\nindex 9d74653cf..0d7bf2c9e 100644\n--- a/lib/librte_fib/dir24_8.c\n+++ b/lib/librte_fib/dir24_8.c\n@@ -18,6 +18,12 @@\n #include <rte_fib.h>\n #include \"dir24_8.h\"\n \n+#ifdef CC_DIR24_8_AVX512_SUPPORT\n+\n+#include \"dir24_8_avx512.h\"\n+\n+#endif /* CC_DIR24_8_AVX512_SUPPORT */\n+\n #define DIR24_8_NAMESIZE\t64\n \n #define ROUNDUP(x, y)\t RTE_ALIGN_CEIL(x, (1 << (32 - y)))\n@@ -62,6 +68,24 @@ dir24_8_get_lookup_fn(void *p, enum rte_fib_dir24_8_lookup_type type)\n \t\t}\n \tcase RTE_FIB_DIR24_8_SCALAR_UNI:\n \t\treturn dir24_8_lookup_bulk_uni;\n+#ifdef CC_DIR24_8_AVX512_SUPPORT\n+\tcase RTE_FIB_DIR24_8_VECTOR_AVX512:\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) <= 0)\n+\t\t\treturn NULL;\n+\n+\t\tswitch (nh_sz) {\n+\t\tcase RTE_FIB_DIR24_8_1B:\n+\t\t\treturn rte_dir24_8_vec_lookup_bulk_1b;\n+\t\tcase RTE_FIB_DIR24_8_2B:\n+\t\t\treturn rte_dir24_8_vec_lookup_bulk_2b;\n+\t\tcase RTE_FIB_DIR24_8_4B:\n+\t\t\treturn rte_dir24_8_vec_lookup_bulk_4b;\n+\t\tcase RTE_FIB_DIR24_8_8B:\n+\t\t\treturn rte_dir24_8_vec_lookup_bulk_8b;\n+\t\tdefault:\n+\t\t\treturn NULL;\n+\t\t}\n+#endif\n \tdefault:\n \t\treturn NULL;\n \t}\ndiff --git a/lib/librte_fib/dir24_8_avx512.c b/lib/librte_fib/dir24_8_avx512.c\nnew file mode 100644\nindex 000000000..43dba28cf\n--- /dev/null\n+++ b/lib/librte_fib/dir24_8_avx512.c\n@@ -0,0 +1,165 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#include <rte_vect.h>\n+#include <rte_fib.h>\n+\n+#include \"dir24_8.h\"\n+#include \"dir24_8_avx512.h\"\n+\n+static __rte_always_inline void\n+dir24_8_vec_lookup_x16(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, int size)\n+{\n+\tstruct dir24_8_tbl *dp = (struct dir24_8_tbl *)p;\n+\t__mmask16 msk_ext;\n+\t__mmask16 exp_msk = 0x5555;\n+\t__m512i ip_vec, idxes, res, bytes;\n+\tconst __m512i zero = _mm512_set1_epi32(0);\n+\tconst __m512i lsb = _mm512_set1_epi32(1);\n+\tconst __m512i lsbyte_msk = _mm512_set1_epi32(0xff);\n+\t__m512i tmp1, tmp2, res_msk;\n+\t__m256i tmp256;\n+\t/* used to mask gather values if size is 1/2 (8/16 bit next hops) */\n+\tif (size == sizeof(uint8_t))\n+\t\tres_msk = _mm512_set1_epi32(UINT8_MAX);\n+\telse if (size == sizeof(uint16_t))\n+\t\tres_msk = _mm512_set1_epi32(UINT16_MAX);\n+\n+\tip_vec = _mm512_loadu_si512(ips);\n+\t/* mask 24 most significant bits */\n+\tidxes = _mm512_srli_epi32(ip_vec, 8);\n+\n+\t/**\n+\t * lookup in tbl24\n+\t * Put it inside branch to make compiler happy with -O0\n+\t */\n+\tif (size == sizeof(uint8_t)) {\n+\t\tres = _mm512_i32gather_epi32(idxes, (const int *)dp->tbl24, 1);\n+\t\tres = _mm512_and_epi32(res, res_msk);\n+\t} else if (size == sizeof(uint16_t)) {\n+\t\tres = _mm512_i32gather_epi32(idxes, (const int *)dp->tbl24, 2);\n+\t\tres = _mm512_and_epi32(res, res_msk);\n+\t} else\n+\t\tres = _mm512_i32gather_epi32(idxes, (const int *)dp->tbl24, 4);\n+\n+\t/* get extended entries indexes */\n+\tmsk_ext = _mm512_test_epi32_mask(res, lsb);\n+\n+\tif (msk_ext != 0) {\n+\t\tidxes = _mm512_srli_epi32(res, 1);\n+\t\tidxes = _mm512_slli_epi32(idxes, 8);\n+\t\tbytes = _mm512_and_epi32(ip_vec, lsbyte_msk);\n+\t\tidxes = _mm512_maskz_add_epi32(msk_ext, idxes, bytes);\n+\t\tif (size == sizeof(uint8_t)) {\n+\t\t\tidxes = _mm512_mask_i32gather_epi32(zero, msk_ext,\n+\t\t\t\tidxes, (const int *)dp->tbl8, 1);\n+\t\t\tidxes = _mm512_and_epi32(idxes, res_msk);\n+\t\t} else if (size == sizeof(uint16_t)) {\n+\t\t\tidxes = _mm512_mask_i32gather_epi32(zero, msk_ext,\n+\t\t\t\tidxes, (const int *)dp->tbl8, 2);\n+\t\t\tidxes = _mm512_and_epi32(idxes, res_msk);\n+\t\t} else\n+\t\t\tidxes = _mm512_mask_i32gather_epi32(zero, msk_ext,\n+\t\t\t\tidxes, (const int *)dp->tbl8, 4);\n+\n+\t\tres = _mm512_mask_blend_epi32(msk_ext, res, idxes);\n+\t}\n+\n+\tres = _mm512_srli_epi32(res, 1);\n+\ttmp1 = _mm512_maskz_expand_epi32(exp_msk, res);\n+\ttmp256 = _mm512_extracti32x8_epi32(res, 1);\n+\ttmp2 = _mm512_maskz_expand_epi32(exp_msk,\n+\t\t_mm512_castsi256_si512(tmp256));\n+\t_mm512_storeu_si512(next_hops, tmp1);\n+\t_mm512_storeu_si512(next_hops + 8, tmp2);\n+}\n+\n+static __rte_always_inline void\n+dir24_8_vec_lookup_x8_8b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops)\n+{\n+\tstruct dir24_8_tbl *dp = (struct dir24_8_tbl *)p;\n+\tconst __m512i zero = _mm512_set1_epi32(0);\n+\tconst __m512i lsbyte_msk = _mm512_set1_epi64(0xff);\n+\tconst __m512i lsb = _mm512_set1_epi64(1);\n+\t__m512i res, idxes, bytes;\n+\t__m256i idxes_256, ip_vec;\n+\t__mmask8 msk_ext;\n+\n+\tip_vec = _mm256_loadu_si256((const void *)ips);\n+\t/* mask 24 most significant bits */\n+\tidxes_256 = _mm256_srli_epi32(ip_vec, 8);\n+\n+\t/* lookup in tbl24 */\n+\tres = _mm512_i32gather_epi64(idxes_256, (const void *)dp->tbl24, 8);\n+\n+\t/* get extended entries indexes */\n+\tmsk_ext = _mm512_test_epi64_mask(res, lsb);\n+\n+\tif (msk_ext != 0) {\n+\t\tbytes = _mm512_cvtepi32_epi64(ip_vec);\n+\t\tidxes = _mm512_srli_epi64(res, 1);\n+\t\tidxes = _mm512_slli_epi64(idxes, 8);\n+\t\tbytes = _mm512_and_epi64(bytes, lsbyte_msk);\n+\t\tidxes = _mm512_maskz_add_epi64(msk_ext, idxes, bytes);\n+\t\tidxes = _mm512_mask_i64gather_epi64(zero, msk_ext, idxes,\n+\t\t\t(const void *)dp->tbl8, 8);\n+\n+\t\tres = _mm512_mask_blend_epi64(msk_ext, res, idxes);\n+\t}\n+\n+\tres = _mm512_srli_epi64(res, 1);\n+\t_mm512_storeu_si512(next_hops, res);\n+}\n+\n+void\n+rte_dir24_8_vec_lookup_bulk_1b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, const unsigned int n)\n+{\n+\tuint32_t i;\n+\tfor (i = 0; i < (n / 16); i++)\n+\t\tdir24_8_vec_lookup_x16(p, ips + i * 16, next_hops + i * 16,\n+\t\t\tsizeof(uint8_t));\n+\n+\tdir24_8_lookup_bulk_1b(p, ips + i * 16, next_hops + i * 16,\n+\t\tn - i * 16);\n+}\n+\n+void\n+rte_dir24_8_vec_lookup_bulk_2b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, const unsigned int n)\n+{\n+\tuint32_t i;\n+\tfor (i = 0; i < (n / 16); i++)\n+\t\tdir24_8_vec_lookup_x16(p, ips + i * 16, next_hops + i * 16,\n+\t\t\tsizeof(uint16_t));\n+\n+\tdir24_8_lookup_bulk_2b(p, ips + i * 16, next_hops + i * 16,\n+\t\tn - i * 16);\n+}\n+\n+void\n+rte_dir24_8_vec_lookup_bulk_4b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, const unsigned int n)\n+{\n+\tuint32_t i;\n+\tfor (i = 0; i < (n / 16); i++)\n+\t\tdir24_8_vec_lookup_x16(p, ips + i * 16, next_hops + i * 16,\n+\t\t\tsizeof(uint32_t));\n+\n+\tdir24_8_lookup_bulk_4b(p, ips + i * 16, next_hops + i * 16,\n+\t\tn - i * 16);\n+}\n+\n+void\n+rte_dir24_8_vec_lookup_bulk_8b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, const unsigned int n)\n+{\n+\tuint32_t i;\n+\tfor (i = 0; i < (n / 8); i++)\n+\t\tdir24_8_vec_lookup_x8_8b(p, ips + i * 8, next_hops + i * 8);\n+\n+\tdir24_8_lookup_bulk_8b(p, ips + i * 8, next_hops + i * 8, n - i * 8);\n+}\ndiff --git a/lib/librte_fib/dir24_8_avx512.h b/lib/librte_fib/dir24_8_avx512.h\nnew file mode 100644\nindex 000000000..1d3c2b931\n--- /dev/null\n+++ b/lib/librte_fib/dir24_8_avx512.h\n@@ -0,0 +1,24 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#ifndef _DIR248_AVX512_H_\n+#define _DIR248_AVX512_H_\n+\n+void\n+rte_dir24_8_vec_lookup_bulk_1b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, const unsigned int n);\n+\n+void\n+rte_dir24_8_vec_lookup_bulk_2b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, const unsigned int n);\n+\n+void\n+rte_dir24_8_vec_lookup_bulk_4b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, const unsigned int n);\n+\n+void\n+rte_dir24_8_vec_lookup_bulk_8b(void *p, const uint32_t *ips,\n+\tuint64_t *next_hops, const unsigned int n);\n+\n+#endif /* _DIR248_AVX512_H_ */\ndiff --git a/lib/librte_fib/meson.build b/lib/librte_fib/meson.build\nindex 771828fbe..d96ff0288 100644\n--- a/lib/librte_fib/meson.build\n+++ b/lib/librte_fib/meson.build\n@@ -5,3 +5,21 @@\n sources = files('rte_fib.c', 'rte_fib6.c', 'dir24_8.c', 'trie.c')\n headers = files('rte_fib.h', 'rte_fib6.h')\n deps += ['rib']\n+\n+if arch_subdir == 'x86' and not machine_args.contains('-mno-avx512f')\n+\t# compile AVX512 version if either:\n+\t# a. we have AVX512F supported in minimum instruction set baseline\n+\t# b. it's not minimum instruction set, but supported by compiler\n+\tif dpdk_conf.has('RTE_MACHINE_CPUFLAG_AVX512F')\n+\t\tcflags += ['-DCC_DIR24_8_AVX512_SUPPORT']\n+\t\tsources += files('dir24_8_avx512.c')\n+\telif cc.has_multi_arguments('-mavx512f', '-mavx512dq')\n+\t\tdir24_8_avx512_tmp = static_library('dir24_8_avx512_tmp',\n+\t\t\t\t'dir24_8_avx512.c',\n+\t\t\t\tdependencies: static_rte_eal,\n+\t\t\t\tc_args: cflags + ['-mavx512f', '-mavx512dq'])\n+\t\tobjs += dir24_8_avx512_tmp.extract_objects('dir24_8_avx512.c')\n+\t\tcflags += '-DCC_DIR24_8_AVX512_SUPPORT'\n+\tendif\n+endif\n+\ndiff --git a/lib/librte_fib/rte_fib.h b/lib/librte_fib/rte_fib.h\nindex 892898c6f..4a348670d 100644\n--- a/lib/librte_fib/rte_fib.h\n+++ b/lib/librte_fib/rte_fib.h\n@@ -61,7 +61,8 @@ enum rte_fib_dir24_8_nh_sz {\n enum rte_fib_dir24_8_lookup_type {\n \tRTE_FIB_DIR24_8_SCALAR_MACRO,\n \tRTE_FIB_DIR24_8_SCALAR_INLINE,\n-\tRTE_FIB_DIR24_8_SCALAR_UNI\n+\tRTE_FIB_DIR24_8_SCALAR_UNI,\n+\tRTE_FIB_DIR24_8_VECTOR_AVX512\n };\n \n /** FIB configuration structure */\n", "prefixes": [ "v7", "4/8" ] }