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GET /api/patches/71925/?format=api
http://patches.dpdk.org/api/patches/71925/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200622064634.70941-59-guinanx.sun@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200622064634.70941-59-guinanx.sun@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200622064634.70941-59-guinanx.sun@intel.com", "date": "2020-06-22T06:46:22", "name": "[58/70] net/e1000/base: add PHY power management control", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "da03f9fe5c004c8633e45077c03f9d31f4f6b7df", "submitter": { "id": 1476, "url": "http://patches.dpdk.org/api/people/1476/?format=api", "name": "Guinan Sun", "email": "guinanx.sun@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200622064634.70941-59-guinanx.sun@intel.com/mbox/", "series": [ { "id": 10543, "url": "http://patches.dpdk.org/api/series/10543/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10543", "date": "2020-06-22T06:45:24", "name": "update e1000 base code", "version": 1, "mbox": "http://patches.dpdk.org/series/10543/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/71925/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/71925/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E74ABA0350;\n\tMon, 22 Jun 2020 09:16:08 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2ABD71D5EC;\n\tMon, 22 Jun 2020 09:07:14 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id 1AA7A1C1AA\n for <dev@dpdk.org>; Mon, 22 Jun 2020 09:07:08 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 22 Jun 2020 00:07:08 -0700", "from dpdk.sh.intel.com ([10.239.255.83])\n by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2020 00:07:07 -0700" ], "IronPort-SDR": [ "\n afa1VWmtdXERfbOpFTiT96/hIdC2FgALMUyWIWxrGpt5l6qe359rCXIyco49gyyL71luB3YnZZ\n SFjvxjR7M5hg==", "\n rwTz7mqVZx5fcDwE17cXSyscpmSDMkeu86CfLL/vMLCsKe3XsADQleFAEADI7o2pmVtGqMpUXh\n 9oy7fOPJPiuA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9659\"; a=\"131070867\"", "E=Sophos;i=\"5.75,266,1589266800\"; d=\"scan'208\";a=\"131070867\"", "E=Sophos;i=\"5.75,266,1589266800\"; d=\"scan'208\";a=\"384409254\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Guinan Sun <guinanx.sun@intel.com>", "To": "dev@dpdk.org", "Cc": "Jeff Guo <jia.guo@intel.com>, Zhao1 Wei <wei.zhao1@intel.com>,\n Guinan Sun <guinanx.sun@intel.com>, Sasha Neftin <sasha.neftin@intel.com>", "Date": "Mon, 22 Jun 2020 06:46:22 +0000", "Message-Id": "<20200622064634.70941-59-guinanx.sun@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200622064634.70941-1-guinanx.sun@intel.com>", "References": "<20200622064634.70941-1-guinanx.sun@intel.com>", "Subject": "[dpdk-dev] [PATCH 58/70] net/e1000/base: add PHY power management\n\tcontrol", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "PHY power management control should provide a reliable and accurate\nindication of PHY reset completion and decrease the delay time\nafter a PHY reset.\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\nSigned-off-by: Guinan Sun <guinanx.sun@intel.com>\n---\n drivers/net/e1000/base/e1000_defines.h | 4 ++++\n drivers/net/e1000/base/e1000_phy.c | 12 +++++++++++-\n 2 files changed, 15 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/e1000/base/e1000_defines.h b/drivers/net/e1000/base/e1000_defines.h\nindex 00afdaa25..effd04dfd 100644\n--- a/drivers/net/e1000/base/e1000_defines.h\n+++ b/drivers/net/e1000/base/e1000_defines.h\n@@ -1100,8 +1100,12 @@\n #define ANEG_MULTIGBT_AN_CTRL\t0x0020 /* MULTI GBT AN Control Register */\n #define MMD_DEVADDR_SHIFT\t16 /* Shift MMD to higher bits */\n #define CR_2500T_FD_CAPS\t0x0080 /* Advertise 2500T FD capability */\n+\n #define PHY_CONTROL_LB\t\t0x4000 /* PHY Loopback bit */\n \n+\n+#define E1000_PHY_RST_COMP\t0x0100 /* Internal PHY reset completion */\n+\n /* NVM Control */\n #define E1000_EECD_SK\t\t0x00000001 /* NVM Clock */\n #define E1000_EECD_CS\t\t0x00000002 /* NVM Chip Select */\ndiff --git a/drivers/net/e1000/base/e1000_phy.c b/drivers/net/e1000/base/e1000_phy.c\nindex b9d8739ee..712ec1269 100644\n--- a/drivers/net/e1000/base/e1000_phy.c\n+++ b/drivers/net/e1000/base/e1000_phy.c\n@@ -2877,6 +2877,7 @@ s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)\n s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)\n {\n \tstruct e1000_phy_info *phy = &hw->phy;\n+\tu32 phpm = 0, timeout = 10000;\n \ts32 ret_val;\n \tu32 ctrl;\n \n@@ -2892,6 +2893,7 @@ s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)\n \tif (ret_val)\n \t\treturn ret_val;\n \n+\tphpm = E1000_READ_REG(hw, E1000_I225_PHPM);\n \tctrl = E1000_READ_REG(hw, E1000_CTRL);\n \tE1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);\n \tE1000_WRITE_FLUSH(hw);\n@@ -2901,7 +2903,15 @@ s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)\n \tE1000_WRITE_REG(hw, E1000_CTRL, ctrl);\n \tE1000_WRITE_FLUSH(hw);\n \n-\tusec_delay(150);\n+\t/* SW should guarantee 100us for the completion of the PHY reset */\n+\tusec_delay(100);\n+\tdo {\n+\t\tphpm = E1000_READ_REG(hw, E1000_I225_PHPM);\n+\t\ttimeout--;\n+\t\tusec_delay(1);\n+\t} while (!(phpm & E1000_PHY_RST_COMP) && timeout);\n+\n+\tusec_delay(100);\n \n \tphy->ops.release(hw);\n \n", "prefixes": [ "58/70" ] }{ "id": 71925, "url": "