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put:
Update a patch.

GET /api/patches/71892/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 71892,
    "url": "http://patches.dpdk.org/api/patches/71892/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200622064634.70941-26-guinanx.sun@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200622064634.70941-26-guinanx.sun@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200622064634.70941-26-guinanx.sun@intel.com",
    "date": "2020-06-22T06:45:49",
    "name": "[25/70] net/e1000/base: wrap the e1000 defines.h",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "efaa0c548790b85d9d7b2fd484c642553e5227e1",
    "submitter": {
        "id": 1476,
        "url": "http://patches.dpdk.org/api/people/1476/?format=api",
        "name": "Guinan Sun",
        "email": "guinanx.sun@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200622064634.70941-26-guinanx.sun@intel.com/mbox/",
    "series": [
        {
            "id": 10543,
            "url": "http://patches.dpdk.org/api/series/10543/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10543",
            "date": "2020-06-22T06:45:24",
            "name": "update e1000 base code",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/10543/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/71892/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/71892/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AE4BDA0350;\n\tMon, 22 Jun 2020 09:09:56 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3C23D1D44E;\n\tMon, 22 Jun 2020 09:06:05 +0200 (CEST)",
            "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 3B8B21C19C\n for <dev@dpdk.org>; Mon, 22 Jun 2020 09:06:03 +0200 (CEST)",
            "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 22 Jun 2020 00:06:02 -0700",
            "from dpdk.sh.intel.com ([10.239.255.83])\n by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2020 00:06:01 -0700"
        ],
        "IronPort-SDR": [
            "\n 2+lokzha5RtX7cgDpAdBiOLP7KDEDlGScvmXylwhmVnH/6UJf7dQ8C/ptTBgxx8qG7qTlAo1K5\n 1+jbdSFU68gQ==",
            "\n 9dP6Lki0/9tteIOZey7WdCOuQ03CKzGQ4cLn0M5hXzq7P7ExKREnOs8wYU56ku0Yh8smXOMuLl\n vCkM44qL2f3w=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9659\"; a=\"141944817\"",
            "E=Sophos;i=\"5.75,266,1589266800\"; d=\"scan'208\";a=\"141944817\"",
            "E=Sophos;i=\"5.75,266,1589266800\"; d=\"scan'208\";a=\"384408937\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Guinan Sun <guinanx.sun@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Jeff Guo <jia.guo@intel.com>, Zhao1 Wei <wei.zhao1@intel.com>,\n Guinan Sun <guinanx.sun@intel.com>, Sasha Neftin <sasha.neftin@intel.com>",
        "Date": "Mon, 22 Jun 2020 06:45:49 +0000",
        "Message-Id": "<20200622064634.70941-26-guinanx.sun@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20200622064634.70941-1-guinanx.sun@intel.com>",
        "References": "<20200622064634.70941-1-guinanx.sun@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 25/70] net/e1000/base: wrap the e1000 defines.h",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Allow the e1000_defines.h to be processed by build.mk and be\nclosest as possible to the upstream igc_defines.h file\n\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\nSigned-off-by: Guinan Sun <guinanx.sun@intel.com>\n---\n drivers/net/e1000/base/e1000_defines.h | 18 ++++++++++++++++--\n 1 file changed, 16 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/e1000/base/e1000_defines.h b/drivers/net/e1000/base/e1000_defines.h\nindex 03006cd6e..341d66daf 100644\n--- a/drivers/net/e1000/base/e1000_defines.h\n+++ b/drivers/net/e1000/base/e1000_defines.h\n@@ -411,6 +411,10 @@\n #define E1000_RXCSUM_IPPCSE\t0x00001000 /* IP payload checksum enable */\n #define E1000_RXCSUM_PCSD\t0x00002000 /* packet checksum disabled */\n \n+/* GPY211 - I225 defines */\n+#define GPY_MMD_MASK\t\t0xFFFF0000\n+#define GPY_MMD_SHIFT\t\t16\n+#define GPY_REG_MASK\t\t0x0000FFFF\n /* Header split receive */\n #define E1000_RFCTL_NFSW_DIS\t\t0x00000040\n #define E1000_RFCTL_NFSR_DIS\t\t0x00000080\n@@ -421,8 +425,8 @@\n #define E1000_RFCTL_LEF\t\t\t0x00040000\n \n /* Collision related configuration parameters */\n-#define E1000_COLLISION_THRESHOLD\t15\n #define E1000_CT_SHIFT\t\t\t4\n+#define E1000_COLLISION_THRESHOLD\t15\n #define E1000_COLLISION_DISTANCE\t63\n #define E1000_COLD_SHIFT\t\t12\n \n@@ -593,6 +597,8 @@\n #define E1000_IMS_VMMB\t\tE1000_ICR_VMMB    /* Mail box activity */\n #define E1000_IMS_RXSEQ\t\tE1000_ICR_RXSEQ   /* Rx sequence error */\n #define E1000_IMS_RXDMT0\tE1000_ICR_RXDMT0  /* Rx desc min. threshold */\n+#define E1000_QVECTOR_MASK\t0x7FFC\t\t/* Q-vector mask */\n+#define E1000_ITR_VAL_MASK\t0x04\t\t/* ITR value mask */\n #define E1000_IMS_RXO\t\tE1000_ICR_RXO     /* Rx overrun */\n #define E1000_IMS_RXT0\t\tE1000_ICR_RXT0    /* Rx timer intr */\n #define E1000_IMS_TXD_LOW\tE1000_ICR_TXD_LOW\n@@ -625,6 +631,7 @@\n #define E1000_ICS_LSC\t\tE1000_ICR_LSC       /* Link Status Change */\n #define E1000_ICS_RXSEQ\t\tE1000_ICR_RXSEQ     /* Rx sequence error */\n #define E1000_ICS_RXDMT0\tE1000_ICR_RXDMT0    /* Rx desc min. threshold */\n+#define E1000_ICS_DRSTA\t\tIGC_ICR_DRSTA     /* Device Reset Aserted */\n \n /* Extended Interrupt Cause Set */\n #define E1000_EICS_RX_QUEUE0\tE1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */\n@@ -820,7 +827,7 @@\n #define E1000_THSTAT_PWR_DOWN\t\t0x00000001 /* Power Down Event */\n #define E1000_THSTAT_LINK_THROTTLE\t0x00000002 /* Link Spd Throttle Event */\n \n-/* I350 EEE defines */\n+/* EEE defines */\n #define E1000_IPCNFG_EEE_2_5G_AN\t0x00000010 /* IPCNFG EEE Ena 2.5G AN */\n #define E1000_IPCNFG_EEE_1G_AN\t\t0x00000008 /* IPCNFG EEE Ena 1G AN */\n #define E1000_IPCNFG_EEE_100M_AN\t0x00000004 /* IPCNFG EEE Ena 100M AN */\n@@ -1396,6 +1403,8 @@\n #define GG82563_PHY_INBAND_CTRL\t\tGG82563_REG(194, 18) /* Inband Ctrl */\n \n /* MDI Control */\n+#define E1000_MDIC_DATA_MASK\t0x0000FFFF\n+#define E1000_MDIC_INT_EN\t0x20000000\n #define E1000_MDIC_REG_MASK\t0x001F0000\n #define E1000_MDIC_REG_SHIFT\t16\n #define E1000_MDIC_PHY_MASK\t0x03E00000\n@@ -1406,6 +1415,11 @@\n #define E1000_MDIC_ERROR\t0x40000000\n #define E1000_MDIC_DEST\t\t0x80000000\n \n+#define E1000_N0_QUEUE -1\n+\n+#define E1000_MAX_MAC_HDR_LEN\t127\n+#define E1000_MAX_NETWORK_HDR_LEN\t511\n+\n /* SerDes Control */\n #define E1000_GEN_CTL_READY\t\t0x80000000\n #define E1000_GEN_CTL_ADDRESS_SHIFT\t8\n",
    "prefixes": [
        "25/70"
    ]
}