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GET /api/patches/71854/?format=api
{ "id": 71854, "url": "http://patches.dpdk.org/api/patches/71854/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200621191200.28120-4-parav@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200621191200.28120-4-parav@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200621191200.28120-4-parav@mellanox.com", "date": "2020-06-21T19:11:57", "name": "[v2,3/6] bus/mlx5_pci: add mlx5 PCI bus", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9c853527da0a0bdcc11f23378e3e11a3f903ec32", "submitter": { "id": 1780, "url": "http://patches.dpdk.org/api/people/1780/?format=api", "name": "Parav Pandit", "email": "parav@mellanox.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200621191200.28120-4-parav@mellanox.com/mbox/", "series": [ { "id": 10537, "url": "http://patches.dpdk.org/api/series/10537/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10537", "date": "2020-06-21T19:11:54", "name": "Improve mlx5 PMD common driver framework for multiple classes", "version": 2, "mbox": "http://patches.dpdk.org/series/10537/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/71854/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/71854/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=EQT/FjrJshnwnjZo4jVrB/UG4PdFcXD16To2/hMRfrxqlM5dz72pKrcvISe1b7ndj4Q7au6tI7hBPW81I/Z6rGIFxvwuGNUFMiak+REVVfMuhkVskkOAa0sdzXE+YfuKSafIF2FoBXU/DEyzUxFsFa7XcoHQCtHG27B1l4LqsoE=", "Authentication-Results": "u256.net; dkim=none (message not signed)\n header.d=none;u256.net; dmarc=none action=none header.from=mellanox.com;", "From": "Parav Pandit <parav@mellanox.com>", "To": "grive@u256.net, ferruh.yigit@intel.com, thomas@monjalon.net, dev@dpdk.org", "Cc": "orika@mellanox.com, matan@mellanox.com, Parav Pandit <parav@mellanox.com>", "Date": "Sun, 21 Jun 2020 19:11:57 +0000", "Message-Id": "<20200621191200.28120-4-parav@mellanox.com>", "X-Mailer": [ "git-send-email 2.25.4", "git-send-email 2.25.4" ], "In-Reply-To": "<20200621191200.28120-1-parav@mellanox.com>", "References": "<20200610171728.89-2-parav@mellanox.com>\n <20200621191200.28120-1-parav@mellanox.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "DM6PR02CA0105.namprd02.prod.outlook.com\n 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sJBpL9wZ7GEbNneL9sCG3ybtXpU1cy+udK3a6vYaX8gXueBDPNsAe+5Jb1pzcvD+w83Y+wiL7rhG21xNsCgb0HofLjItfa53ReKxir2SdU72LB086tbIWeVXBBuXzfu6qGdVtX8+NgfyPbnBV0uhY2RI2FdCCjJqHEq3+muCd7FvU9Edxgh1UuK/e2eVrOGq/7hIPtkOxSvPlhLz1mIaIv3w5mc/BQxHihOaKZHXFpzAKLKluHp01e917PurisztnY4TAcs0/AfoHjt7cFDjiriGotDko9nCsgG7HT1psCza+4a/goN0C+vGdF0MHoW5kmz3TOfU9i9Faaa6IPJWlvtZx6fsSTRdt2zSw16hjHlxJdg6kHS3LNebB09d6IxjA9jLccgGMaAYGeICgMOS1iffIls+K47Eh8X6uyje/PRK2UQVvK6SAps1Sne7Ekr07E3bV2yCCLlSNPzteGJ0sOlueAFeizhJtBYfB6qUQzXDvjzrW0o+i9Nbr+y12U5U", "X-OriginatorOrg": "Mellanox.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 25ccd952-9466-4029-9e4a-08d816170707", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Jun 2020 19:12:23.4182 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "a652971c-7d2e-4d9b-a6a4-d149256f461b", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n UfCbFRHRK4faOvowQaDBnO6uDvuPw/5iK7TldoMvM+Gdleqv3kBiqPBg4oJ1J25yoL9nQqkCxJjhYY9G7CaHqw==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM0PR05MB6307", "Subject": "[dpdk-dev] [PATCH v2 3/6] bus/mlx5_pci: add mlx5 PCI bus", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add mlx5 PCI bus which enables multiple mlx5 drivers to bind to single\npci device.\n\nSigned-off-by: Parav Pandit <parav@mellanox.com>\n---\nChangelog:\nv1->v2:\n - Address comments from Thomas and Gaetan\n - Inheriting ret_pci_driver instead of rte_driver\n - Added design and description of the mlx5_pci bus\n---\n config/common_base | 6 ++\n config/defconfig_arm64-bluefield-linuxapp-gcc | 6 ++\n drivers/bus/meson.build | 2 +-\n drivers/bus/mlx5_pci/Makefile | 47 +++++++++++\n drivers/bus/mlx5_pci/meson.build | 6 ++\n drivers/bus/mlx5_pci/mlx5_pci_bus.c | 14 ++++\n drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h | 84 +++++++++++++++++++\n .../bus/mlx5_pci/rte_bus_mlx5_pci_version.map | 5 ++\n 8 files changed, 169 insertions(+), 1 deletion(-)\n create mode 100644 drivers/bus/mlx5_pci/Makefile\n create mode 100644 drivers/bus/mlx5_pci/meson.build\n create mode 100644 drivers/bus/mlx5_pci/mlx5_pci_bus.c\n create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\n create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map", "diff": "diff --git a/config/common_base b/config/common_base\nindex c7d5c7321..f75b333f9 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -366,6 +366,12 @@ CONFIG_RTE_LIBRTE_IGC_DEBUG_TX=n\n CONFIG_RTE_LIBRTE_MLX4_PMD=n\n CONFIG_RTE_LIBRTE_MLX4_DEBUG=n\n \n+#\n+# Compile Mellanox PCI BUS for ConnectX-4, ConnectX-5,\n+# ConnectX-6 & BlueField (MLX5) PMD\n+#\n+CONFIG_RTE_LIBRTE_MLX5_PCI_BUS=n\n+\n #\n # Compile burst-oriented Mellanox ConnectX-4, ConnectX-5,\n # ConnectX-6 & BlueField (MLX5) PMD\ndiff --git a/config/defconfig_arm64-bluefield-linuxapp-gcc b/config/defconfig_arm64-bluefield-linuxapp-gcc\nindex b49653881..15ade7ebc 100644\n--- a/config/defconfig_arm64-bluefield-linuxapp-gcc\n+++ b/config/defconfig_arm64-bluefield-linuxapp-gcc\n@@ -14,5 +14,11 @@ CONFIG_RTE_CACHE_LINE_SIZE=64\n CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n\n CONFIG_RTE_LIBRTE_VHOST_NUMA=n\n \n+#\n+# Compile Mellanox PCI BUS for ConnectX-4, ConnectX-5,\n+# ConnectX-6 & BlueField (MLX5) PMD\n+#\n+CONFIG_RTE_LIBRTE_MLX5_PCI_BUS=n\n+\n # PMD for ConnectX-5\n CONFIG_RTE_LIBRTE_MLX5_PMD=y\ndiff --git a/drivers/bus/meson.build b/drivers/bus/meson.build\nindex 80de2d91d..b1381838d 100644\n--- a/drivers/bus/meson.build\n+++ b/drivers/bus/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n-drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'vdev', 'vmbus']\n+drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'mlx5_pci', 'vdev', 'vmbus']\n std_deps = ['eal']\n config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'\n driver_name_fmt = 'rte_bus_@0@'\ndiff --git a/drivers/bus/mlx5_pci/Makefile b/drivers/bus/mlx5_pci/Makefile\nnew file mode 100644\nindex 000000000..7db977ba8\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/Makefile\n@@ -0,0 +1,47 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright 2020 Mellanox Technologies, Ltd\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_bus_mlx5_pci.a\n+\n+CFLAGS += -O3\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -I$(RTE_SDK)/drivers/common/mlx5\n+CFLAGS += -I$(BUILDDIR)/drivers/common/mlx5\n+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci\n+LDLIBS += -lrte_eal\n+LDLIBS += -lrte_common_mlx5\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+\n+# versioning export map\n+EXPORT_MAP := rte_bus_mlx5_pci_version.map\n+\n+SRCS-y += mlx5_pci_bus.c\n+\n+# DEBUG which is usually provided on the command-line may enable\n+# CONFIG_RTE_LIBRTE_MLX5_DEBUG.\n+ifeq ($(DEBUG),1)\n+CONFIG_RTE_LIBRTE_MLX5_DEBUG := y\n+endif\n+\n+# User-defined CFLAGS.\n+ifeq ($(CONFIG_RTE_LIBRTE_MLX5_DEBUG),y)\n+CFLAGS += -pedantic\n+ifneq ($(CONFIG_RTE_TOOLCHAIN_ICC),y)\n+CFLAGS += -DPEDANTIC\n+endif\n+AUTO_CONFIG_CFLAGS += -Wno-pedantic\n+else\n+CFLAGS += -UPEDANTIC\n+endif\n+\n+#\n+# Export include files\n+#\n+SYMLINK-y-include += rte_bus_mlx5_pci.h\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/bus/mlx5_pci/meson.build b/drivers/bus/mlx5_pci/meson.build\nnew file mode 100644\nindex 000000000..cc4a84e23\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/meson.build\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2020 Mellanox Technologies Ltd\n+\n+deps += ['pci', 'bus_pci', 'common_mlx5']\n+install_headers('rte_bus_mlx5_pci.h')\n+sources = files('mlx5_pci_bus.c')\ndiff --git a/drivers/bus/mlx5_pci/mlx5_pci_bus.c b/drivers/bus/mlx5_pci/mlx5_pci_bus.c\nnew file mode 100644\nindex 000000000..66db3c7b0\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/mlx5_pci_bus.c\n@@ -0,0 +1,14 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#include \"rte_bus_mlx5_pci.h\"\n+\n+static TAILQ_HEAD(mlx5_pci_bus_drv_head, rte_mlx5_pci_driver) drv_list =\n+\t\t\t\tTAILQ_HEAD_INITIALIZER(drv_list);\n+\n+void\n+rte_mlx5_pci_driver_register(struct rte_mlx5_pci_driver *driver)\n+{\n+\tTAILQ_INSERT_TAIL(&drv_list, driver, next);\n+}\ndiff --git a/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\nnew file mode 100644\nindex 000000000..571f7dfd6\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h\n@@ -0,0 +1,84 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2020 Mellanox Technologies, Ltd\n+ */\n+\n+#ifndef _RTE_BUS_MLX5_PCI_H_\n+#define _RTE_BUS_MLX5_PCI_H_\n+\n+/**\n+ * @file\n+ *\n+ * RTE Mellanox PCI Bus Interface\n+ * Mellanox ConnectX PCI device supports multiple class (net/vdpa/regex)\n+ * devices. This bus enables creating such multiple class of devices on a\n+ * single PCI device by allowing to bind multiple class specific device\n+ * driver to attach to mlx5_pci bus driver.\n+ *\n+ * ----------- ------------ -----------------\n+ * | mlx5 | | mlx5 | | mlx5 |\n+ * | net pmd | | vdpa pmd | | new class pmd |\n+ * ----------- ------------ -----------------\n+ * \\ | /\n+ * \\ | /\n+ * \\ ------------- /\n+ * \\______| mlx5 |_____ /\n+ * | pci bus |\n+ * ------------- \n+ * |\n+ * ----------- \n+ * | mlx5 | \n+ * | pci dev | \n+ * ----------- \n+ *\n+ * - mlx5 pci bus driver binds to mlx5 PCI devices defined by PCI\n+ * ID table of all related mlx5 PCI devices.\n+ * - mlx5 class driver such as net, vdpa, regex PMD defines its\n+ * specific PCI ID table and mlx5 bus driver probes matching\n+ * class drivers.\n+ * - mlx5 pci bus driver is cental place that validates supported\n+ * class combinations.\n+ */\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif /* __cplusplus */\n+\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+\n+#include <mlx5_common.h>\n+\n+/**\n+ * A structure describing a mlx5 pci driver.\n+ */\n+struct rte_mlx5_pci_driver {\n+\tenum mlx5_class dev_class;\t\t/**< Class of this driver */\n+\tstruct rte_pci_driver pci_driver;\t/**< Inherit core pci driver. */\n+\tTAILQ_ENTRY(rte_mlx5_pci_driver) next;\n+};\n+\n+/**\n+ * Register a mlx5_pci device driver.\n+ *\n+ * @param driver\n+ * A pointer to a rte_mlx5_pci_driver structure describing the driver\n+ * to be registered.\n+ */\n+__rte_internal\n+void\n+rte_mlx5_pci_driver_register(struct rte_mlx5_pci_driver *driver);\n+\n+#define RTE_PMD_REGISTER_MLX5_PCI(nm, drv)\t\\\n+static const char *mlx5_pci_drvinit_fn_ ## nm;\t\\\n+RTE_INIT(mlx5_pci_drvinit_fn_ ##drv)\t\\\n+{\t\\\n+\t(drv).driver.name = RTE_STR(nm);\t\\\n+\trte_mlx5_pci_driver_register(&drv);\t\\\n+}\t\\\n+RTE_PMD_EXPORT_NAME(nm, __COUNTER__)\n+\n+#ifdef __cplusplus\n+}\n+#endif /* __cplusplus */\n+\n+#endif /* _RTE_BUS_MLX5_PCI_H_ */\ndiff --git a/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map\nnew file mode 100644\nindex 000000000..4cfd3db10\n--- /dev/null\n+++ b/drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map\n@@ -0,0 +1,5 @@\n+INTERNAL {\n+\tglobal:\n+\n+\trte_mlx5_pci_driver_register;\n+};\n", "prefixes": [ "v2", "3/6" ] }