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GET /api/patches/70583/?format=api
{ "id": 70583, "url": "http://patches.dpdk.org/api/patches/70583/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1590483667-10318-5-git-send-email-phil.yang@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1590483667-10318-5-git-send-email-phil.yang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1590483667-10318-5-git-send-email-phil.yang@arm.com", "date": "2020-05-26T09:01:07", "name": "[v5,4/4] eal/atomic: add wrapper for c11 atomic thread fence", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3794299bd951b87507692337487ea2245f550f78", "submitter": { "id": 833, "url": "http://patches.dpdk.org/api/people/833/?format=api", "name": "Phil Yang", "email": "phil.yang@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1590483667-10318-5-git-send-email-phil.yang@arm.com/mbox/", "series": [ { "id": 10237, "url": "http://patches.dpdk.org/api/series/10237/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=10237", "date": "2020-05-26T09:01:03", "name": "generic rte atomic APIs deprecate proposal", "version": 5, "mbox": "http://patches.dpdk.org/series/10237/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/70583/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/70583/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id AF555A04A4;\n\tTue, 26 May 2020 11:02:41 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 31CA21DA2D;\n\tTue, 26 May 2020 11:02:29 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id 417A11DA2D\n for <dev@dpdk.org>; Tue, 26 May 2020 11:02:28 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B980B1FB;\n Tue, 26 May 2020 02:02:27 -0700 (PDT)", "from phil-VirtualBox.shanghai.arm.com\n (phil-VirtualBox.shanghai.arm.com [10.169.109.151])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A3B223F52E;\n Tue, 26 May 2020 02:02:20 -0700 (PDT)" ], "From": "Phil Yang <phil.yang@arm.com>", "To": "dev@dpdk.org", "Cc": "mattias.ronnblom@ericsson.com, mb@smartsharesystems.com,\n stephen@networkplumber.org, thomas@monjalon.net,\n bruce.richardson@intel.com, ferruh.yigit@intel.com, hemant.agrawal@nxp.com,\n jerinj@marvell.com, ktraynor@redhat.com, konstantin.ananyev@intel.com,\n maxime.coquelin@redhat.com, olivier.matz@6wind.com,\n harry.van.haaren@intel.com, erik.g.carrillo@intel.com,\n drc@linux.vnet.ibm.com, david.marchand@redhat.com, zhaoyan.chen@intel.com,\n ola.liljedahl@arm.com, honnappa.nagarahalli@arm.com, ruifeng.wang@arm.com,\n phil.yang@arm.com, nd@arm.com", "Date": "Tue, 26 May 2020 17:01:07 +0800", "Message-Id": "<1590483667-10318-5-git-send-email-phil.yang@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1590483667-10318-1-git-send-email-phil.yang@arm.com>", "References": "<1589270586-4480-1-git-send-email-phil.yang@arm.com>\n <1590483667-10318-1-git-send-email-phil.yang@arm.com>", "Subject": "[dpdk-dev] [PATCH v5 4/4] eal/atomic: add wrapper for c11 atomic\n\tthread fence", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Provide a wrapper for __atomic_thread_fence built-in to support\noptimized code for __ATOMIC_SEQ_CST memory order for x86 platforms.\n\nSuggested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nReviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>\n---\n lib/librte_eal/arm/include/rte_atomic_32.h | 6 ++++++\n lib/librte_eal/arm/include/rte_atomic_64.h | 6 ++++++\n lib/librte_eal/include/generic/rte_atomic.h | 6 ++++++\n lib/librte_eal/ppc/include/rte_atomic.h | 6 ++++++\n lib/librte_eal/x86/include/rte_atomic.h | 17 +++++++++++++++++\n 5 files changed, 41 insertions(+)", "diff": "diff --git a/lib/librte_eal/arm/include/rte_atomic_32.h b/lib/librte_eal/arm/include/rte_atomic_32.h\nindex 7dc0d06..dbe7cc6 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_32.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_32.h\n@@ -37,6 +37,12 @@ extern \"C\" {\n \n #define rte_cio_rmb() rte_rmb()\n \n+static __rte_always_inline void\n+rte_atomic_thread_fence(int mo)\n+{\n+\t__atomic_thread_fence(mo);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h\nindex 7b7099c..22ff8ec 100644\n--- a/lib/librte_eal/arm/include/rte_atomic_64.h\n+++ b/lib/librte_eal/arm/include/rte_atomic_64.h\n@@ -41,6 +41,12 @@ extern \"C\" {\n \n #define rte_cio_rmb() asm volatile(\"dmb oshld\" : : : \"memory\")\n \n+static __rte_always_inline void\n+rte_atomic_thread_fence(int mo)\n+{\n+\t__atomic_thread_fence(mo);\n+}\n+\n /*------------------------ 128 bit atomic operations -------------------------*/\n \n #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)\ndiff --git a/lib/librte_eal/include/generic/rte_atomic.h b/lib/librte_eal/include/generic/rte_atomic.h\nindex e6ab15a..5b941db 100644\n--- a/lib/librte_eal/include/generic/rte_atomic.h\n+++ b/lib/librte_eal/include/generic/rte_atomic.h\n@@ -158,6 +158,12 @@ static inline void rte_cio_rmb(void);\n \tasm volatile (\"\" : : : \"memory\");\t\\\n } while(0)\n \n+/**\n+ * Synchronization fence between threads based on the specified\n+ * memory order.\n+ */\n+static inline void rte_atomic_thread_fence(int mo);\n+\n /*------------------------- 16 bit atomic operations -------------------------*/\n \n /**\ndiff --git a/lib/librte_eal/ppc/include/rte_atomic.h b/lib/librte_eal/ppc/include/rte_atomic.h\nindex 7e3e131..91c5f30 100644\n--- a/lib/librte_eal/ppc/include/rte_atomic.h\n+++ b/lib/librte_eal/ppc/include/rte_atomic.h\n@@ -40,6 +40,12 @@ extern \"C\" {\n \n #define rte_cio_rmb() rte_rmb()\n \n+static __rte_always_inline void\n+rte_atomic_thread_fence(int mo)\n+{\n+\t__atomic_thread_fence(mo);\n+}\n+\n /*------------------------- 16 bit atomic operations -------------------------*/\n /* To be compatible with Power7, use GCC built-in functions for 16 bit\n * operations */\ndiff --git a/lib/librte_eal/x86/include/rte_atomic.h b/lib/librte_eal/x86/include/rte_atomic.h\nindex b9dcd30..bd256e7 100644\n--- a/lib/librte_eal/x86/include/rte_atomic.h\n+++ b/lib/librte_eal/x86/include/rte_atomic.h\n@@ -83,6 +83,23 @@ rte_smp_mb(void)\n \n #define rte_cio_rmb() rte_compiler_barrier()\n \n+/**\n+ * Synchronization fence between threads based on the specified\n+ * memory order.\n+ *\n+ * On x86 the __atomic_thread_fence(__ATOMIC_SEQ_CST) generates\n+ * full 'mfence' which is quite expensive. The optimized\n+ * implementation of rte_smp_mb is used instead.\n+ */\n+static __rte_always_inline void\n+rte_atomic_thread_fence(int mo)\n+{\n+\tif (mo == __ATOMIC_SEQ_CST)\n+\t\trte_smp_mb();\n+\telse\n+\t\t__atomic_thread_fence(mo);\n+}\n+\n /*------------------------- 16 bit atomic operations -------------------------*/\n \n #ifndef RTE_FORCE_INTRINSICS\n", "prefixes": [ "v5", "4/4" ] }