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GET /api/patches/69458/?format=api
{ "id": 69458, "url": "http://patches.dpdk.org/api/patches/69458/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200428124026.43783-1-kevin.laatz@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200428124026.43783-1-kevin.laatz@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200428124026.43783-1-kevin.laatz@intel.com", "date": "2020-04-28T12:40:26", "name": "[v5] eal/cpuflags: add x86 based cpu flags", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "940009dc302a9e21e2d6404baa9b379441cd61b9", "submitter": { "id": 921, "url": "http://patches.dpdk.org/api/people/921/?format=api", "name": "Kevin Laatz", "email": "kevin.laatz@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200428124026.43783-1-kevin.laatz@intel.com/mbox/", "series": [ { "id": 9707, "url": "http://patches.dpdk.org/api/series/9707/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9707", "date": "2020-04-28T12:40:26", "name": "[v5] eal/cpuflags: add x86 based cpu flags", "version": 5, "mbox": "http://patches.dpdk.org/series/9707/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/69458/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/69458/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 19F44A00BE;\n\tTue, 28 Apr 2020 14:41:13 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 857C71D5BE;\n\tTue, 28 Apr 2020 14:41:12 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by dpdk.org (Postfix) with ESMTP id B0E881D5BE\n for <dev@dpdk.org>; Tue, 28 Apr 2020 14:41:10 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 28 Apr 2020 05:41:09 -0700", "from silpixa00399838.ir.intel.com (HELO\n silpixa00399838.ger.corp.intel.com) ([10.237.222.80])\n by fmsmga008.fm.intel.com with ESMTP; 28 Apr 2020 05:41:07 -0700" ], "IronPort-SDR": [ "\n d0Y054Sp2ZNfkfR2s2jLrsdTJ6pw4lz+dc4WJBDirmzS6BiuBh9safQ+u2q5ghrfUr+dfjpKiH\n wx5iTgdt+sAQ==", "\n A7M6xLWct5ZI1zyTNKc3ENyinjAImrbCubHBYQxleGpZLUzmekQfik8mXhLgVZvFDn9XrLdWA2\n 2kPPGTLjMcug==" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.73,327,1583222400\"; d=\"scan'208\";a=\"249161838\"", "From": "Kevin Laatz <kevin.laatz@intel.com>", "To": "dev@dpdk.org", "Cc": "bruce.richardson@intel.com, harry.van.haaren@intel.com,\n thomas@monjalon.net, ray.kinsella@intel.com, nhorman@tuxdriver.com,\n david.marchand@redhat.com, Kevin Laatz <kevin.laatz@intel.com>", "Date": "Tue, 28 Apr 2020 13:40:26 +0100", "Message-Id": "<20200428124026.43783-1-kevin.laatz@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20200416110040.42819-1-kevin.laatz@intel.com>", "References": "<20200416110040.42819-1-kevin.laatz@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds CPU flags which will enable the detection of ISA\nfeatures available on more recent x86 based CPUs.\n\nThe CPUID leaf information can be found in\nTable 1-2. \"Information Returned by CPUID Instruction\" of this document:\nhttps://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf\n\nThe following CPU flags are added in this patch:\n - AVX-512 doubleword and quadword instructions.\n - AVX-512 integer fused multiply-add instructions.\n - AVX-512 conflict detection instructions.\n - AVX-512 byte and word instructions.\n - AVX-512 vector length instructions.\n - AVX-512 vector bit manipulation instructions.\n - AVX-512 vector bit manipulation 2 instructions.\n - Galois field new instructions.\n - Vector AES instructions.\n - Vector carry-less multiply instructions.\n - AVX-512 vector neural network instructions.\n - AVX-512 for bit algorithm instructions.\n - AVX-512 vector popcount instructions.\n - Cache line demote instructions.\n - Direct store instructions.\n - Direct store 64B instructions.\n - AVX-512 two register intersection instructions.\n\nSigned-off-by: Kevin Laatz <kevin.laatz@intel.com>\nAcked-by: Harry van Haaren <harry.van.haaren@intel.com>\n\n---\nv2:\n - Squashed patch set into single patch.\n\nv3:\n - Add abignore entry for 'rte_cpu_flag_t'.\n\nv4:\n - Updated commit message to reflect updated ISA doc linked.\n - Fixed line wrap for VNNI comment.\n - Rebased on master.\n\nv5:\n - Update abignore entry justification.\n---\n devtools/libabigail.abignore | 5 +++++\n lib/librte_eal/x86/include/rte_cpuflags.h | 19 +++++++++++++++++++\n lib/librte_eal/x86/rte_cpuflags.c | 18 ++++++++++++++++++\n 3 files changed, 42 insertions(+)", "diff": "diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore\nindex a59df8f13..045f436fb 100644\n--- a/devtools/libabigail.abignore\n+++ b/devtools/libabigail.abignore\n@@ -11,3 +11,8 @@\n type_kind = enum\n name = rte_crypto_asym_xform_type\n changed_enumerators = RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END\n+; Ignore this enum update as new flags remain unknown to applications\n+[suppress_type]\n+\ttype_kind = enum\n+\tname = rte_cpu_flag_t\n+\tchanged_enumerators = RTE_CPUFLAG_NUMFLAGS\ndiff --git a/lib/librte_eal/x86/include/rte_cpuflags.h b/lib/librte_eal/x86/include/rte_cpuflags.h\nindex 25ba47b96..c1d20364d 100644\n--- a/lib/librte_eal/x86/include/rte_cpuflags.h\n+++ b/lib/librte_eal/x86/include/rte_cpuflags.h\n@@ -113,6 +113,25 @@ enum rte_cpu_flag_t {\n \t/* (EAX 80000007h) EDX features */\n \tRTE_CPUFLAG_INVTSC, /**< INVTSC */\n \n+\tRTE_CPUFLAG_AVX512DQ, /**< AVX512 Doubleword and Quadword */\n+\tRTE_CPUFLAG_AVX512IFMA, /**< AVX512 Integer Fused Multiply-Add */\n+\tRTE_CPUFLAG_AVX512CD, /**< AVX512 Conflict Detection*/\n+\tRTE_CPUFLAG_AVX512BW, /**< AVX512 Byte and Word */\n+\tRTE_CPUFLAG_AVX512VL, /**< AVX512 Vector Length */\n+\tRTE_CPUFLAG_AVX512VBMI, /**< AVX512 Vector Bit Manipulation */\n+\tRTE_CPUFLAG_AVX512VBMI2, /**< AVX512 Vector Bit Manipulation 2 */\n+\tRTE_CPUFLAG_GFNI, /**< Galois Field New Instructions */\n+\tRTE_CPUFLAG_VAES, /**< Vector AES */\n+\tRTE_CPUFLAG_VPCLMULQDQ, /**< Vector Carry-less Multiply */\n+\tRTE_CPUFLAG_AVX512VNNI,\n+\t/**< AVX512 Vector Neural Network Instructions */\n+\tRTE_CPUFLAG_AVX512BITALG, /**< AVX512 Bit Algorithms */\n+\tRTE_CPUFLAG_AVX512VPOPCNTDQ, /**< AVX512 Vector Popcount */\n+\tRTE_CPUFLAG_CLDEMOTE, /**< Cache Line Demote */\n+\tRTE_CPUFLAG_MOVDIRI, /**< Direct Store Instructions */\n+\tRTE_CPUFLAG_MOVDIR64B, /**< Direct Store Instructions 64B */\n+\tRTE_CPUFLAG_AVX512VP2INTERSECT, /**< AVX512 Two Register Intersection */\n+\n \t/* The last item */\n \tRTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */\n };\ndiff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c\nindex 6492df556..30439e795 100644\n--- a/lib/librte_eal/x86/rte_cpuflags.c\n+++ b/lib/librte_eal/x86/rte_cpuflags.c\n@@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {\n \tFEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)\n \n \tFEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8)\n+\n+\tFEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)\n+\tFEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)\n+\tFEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)\n+\tFEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)\n+\tFEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)\n+\tFEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)\n+\tFEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)\n+\tFEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)\n+\tFEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)\n+\tFEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)\n+\tFEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)\n+\tFEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)\n+\tFEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX, 14)\n+\tFEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)\n+\tFEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)\n+\tFEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)\n+\tFEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)\n };\n \n int\n", "prefixes": [ "v5" ] }