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GET /api/patches/67753/?format=api
{ "id": 67753, "url": "http://patches.dpdk.org/api/patches/67753/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200403085216.32684-10-nithind1988@gmail.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200403085216.32684-10-nithind1988@gmail.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200403085216.32684-10-nithind1988@gmail.com", "date": "2020-04-03T08:52:14", "name": "[v3,09/11] net/octeontx2: add tm debug support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0a812892ac5d9a59963f426bf0a7008722969475", "submitter": { "id": 1268, "url": "http://patches.dpdk.org/api/people/1268/?format=api", "name": "Nithin Dabilpuram", "email": "nithind1988@gmail.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200403085216.32684-10-nithind1988@gmail.com/mbox/", "series": [ { "id": 9188, "url": "http://patches.dpdk.org/api/series/9188/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=9188", "date": "2020-04-03T08:52:05", "name": "net/octeontx2: add traffic manager support", "version": 3, "mbox": "http://patches.dpdk.org/series/9188/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/67753/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/67753/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 67F74A0562;\n\tFri, 3 Apr 2020 10:54:10 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id ACF071C1B1;\n\tFri, 3 Apr 2020 10:52:56 +0200 (CEST)", "from mail-pg1-f180.google.com (mail-pg1-f180.google.com\n [209.85.215.180]) by dpdk.org (Postfix) with ESMTP id AE5D21C1B1\n for <dev@dpdk.org>; Fri, 3 Apr 2020 10:52:54 +0200 (CEST)", "by mail-pg1-f180.google.com with SMTP id x7so3206079pgh.5\n for <dev@dpdk.org>; Fri, 03 Apr 2020 01:52:54 -0700 (PDT)", "from hyd1588t430.marvell.com ([115.113.156.2])\n by smtp.gmail.com with ESMTPSA id s9sm5267899pjr.5.2020.04.03.01.52.51\n (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n Fri, 03 Apr 2020 01:52:53 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n h=from:to:cc:subject:date:message-id:in-reply-to:references;\n bh=JfQCN3xIz2h7uLphzsKQgLLiRpM8vBEkKbARYF334Q0=;\n b=rWQ1oBxHIkhQAT3e63QJufDk9c6oXFndweR5JATcdmmXKXP2Uw1iR1biRgRQBSwjeb\n h/9FqKYBJyhlpLGW0ln7udhFNbUZIvA+eI4ZzsSRM1aZDM6DwB7DK0Aavz2ROD08Ouor\n ni06ReZkLChSMZEGxWUtm9p69ubYclOpMpzdh3wfSF2PlOrcm2SVVtW3QF7sPi1i8byD\n ozGntgmjd6akhY5DFrQaBgYdfnqgSaj8/6ocIXbQ7ZMg7lIme1c0uxJE5za77UtFO49h\n Rhuy2m1aHcuJXWVhj1NhA4CUJly/hQKJ14rcGhrEz2Qsj8QSfoc+BcgMH5H/z9ljTzov\n xJfQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20161025;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references;\n bh=JfQCN3xIz2h7uLphzsKQgLLiRpM8vBEkKbARYF334Q0=;\n b=FkX447XqxDsIYMrd2kNJi0wDz4O4cwzi9dDDSU0WD4DTMv/7FXnuAg7kPpmeD1EODO\n 4rX8IiqkwoT/BD7y2exGx/n5+ckLSaaUM/MX3L2s1UUEB0dMcIK9oC4aRpLSUf2q2Btw\n hMkM6WLc3/vapvP7nPvcSqDJktCvK/Nwr/6gU/Hl3DYnE/igMDn0xzxbbgT9hwhpVlB8\n MIGMmmaaofKq2rJiy0E9B1FyvLlfZ2nKjIh1m244A/FznVay/YupA8XuvCcm5SGjthPR\n jis2POV+nQWv4HfSHV4CmqyyWdikZMMV25Q4aja60h+eP9PmH8fLaPsDfpGpnPkxj2U5\n +9+g==", "X-Gm-Message-State": "AGi0PuYGO+Gn/KQeKqchAZjaBO2vVRPKXFP6TZZHC01ury8kzxjnxZuN\n BrasHrdM7J7nw4gDgFIPXNo=", "X-Google-Smtp-Source": "\n APiQypIpWin0vKEbfGayxyLgMkG8HtYpLeRvluqX/UFq4gtEpncijRCQeJsI0WpMDzpWKQdE8qyEOw==", "X-Received": "by 2002:aa7:87ca:: with SMTP id i10mr7439318pfo.169.1585903973815;\n Fri, 03 Apr 2020 01:52:53 -0700 (PDT)", "From": "Nithin Dabilpuram <nithind1988@gmail.com>", "To": "Jerin Jacob <jerinj@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>,\n Kiran Kumar K <kirankumark@marvell.com>", "Cc": "dev@dpdk.org,\n\tkkanas@marvell.com", "Date": "Fri, 3 Apr 2020 14:22:14 +0530", "Message-Id": "<20200403085216.32684-10-nithind1988@gmail.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20200403085216.32684-1-nithind1988@gmail.com>", "References": "<20200312111907.31555-1-ndabilpuram@marvell.com>\n <20200403085216.32684-1-nithind1988@gmail.com>", "Subject": "[dpdk-dev] [PATCH v3 09/11] net/octeontx2: add tm debug support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nithin Dabilpuram <ndabilpuram@marvell.com>\n\nAdd debug support to TM to dump configured topology\nand registers. Also enable debug dump when sq flush fails.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\n---\n drivers/net/octeontx2/otx2_ethdev.h | 1 +\n drivers/net/octeontx2/otx2_ethdev_debug.c | 311 ++++++++++++++++++++++++++++++\n drivers/net/octeontx2/otx2_tm.c | 9 +-\n drivers/net/octeontx2/otx2_tm.h | 1 +\n 4 files changed, 318 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 6679652..0ef90ce 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -459,6 +459,7 @@ int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,\n \t\t\t struct rte_dev_reg_info *regs);\n int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);\n void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);\n+void otx2_nix_tm_dump(struct otx2_eth_dev *dev);\n \n /* Stats */\n int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_debug.c b/drivers/net/octeontx2/otx2_ethdev_debug.c\nindex c8b4cd5..6d951bc 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_debug.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_debug.c\n@@ -6,6 +6,7 @@\n \n #define nix_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n #define NIX_REG_INFO(reg) {reg, #reg}\n+#define NIX_REG_NAME_SZ 48\n \n struct nix_lf_reg_info {\n \tuint32_t offset;\n@@ -390,9 +391,14 @@ otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev)\n \tint rc, q, rq = eth_dev->data->nb_rx_queues;\n \tint sq = eth_dev->data->nb_tx_queues;\n \tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct npa_aq_enq_rsp *npa_rsp;\n+\tstruct npa_aq_enq_req *npa_aq;\n+\tstruct otx2_npa_lf *npa_lf;\n \tstruct nix_aq_enq_rsp *rsp;\n \tstruct nix_aq_enq_req *aq;\n \n+\tnpa_lf = otx2_npa_lf_obj_get();\n+\n \tfor (q = 0; q < rq; q++) {\n \t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n \t\taq->qidx = q;\n@@ -438,6 +444,36 @@ otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev)\n \t\tnix_dump(\"============== port=%d sq=%d ===============\",\n \t\t\t eth_dev->data->port_id, q);\n \t\tnix_lf_sq_dump(&rsp->sq);\n+\n+\t\tif (!npa_lf) {\n+\t\t\totx2_err(\"NPA LF doesn't exist\");\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\t/* Dump SQB Aura minimal info */\n+\t\tnpa_aq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n+\t\tnpa_aq->aura_id = rsp->sq.sqb_aura;\n+\t\tnpa_aq->ctype = NPA_AQ_CTYPE_AURA;\n+\t\tnpa_aq->op = NPA_AQ_INSTOP_READ;\n+\n+\t\trc = otx2_mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to get sq's sqb_aura context\");\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tnix_dump(\"\\nSQB Aura W0: Pool addr\\t\\t0x%\"PRIx64\"\",\n+\t\t\t npa_rsp->aura.pool_addr);\n+\t\tnix_dump(\"SQB Aura W1: ena\\t\\t\\t%d\",\n+\t\t\t npa_rsp->aura.ena);\n+\t\tnix_dump(\"SQB Aura W2: count\\t\\t%\"PRIx64\"\",\n+\t\t\t (uint64_t)npa_rsp->aura.count);\n+\t\tnix_dump(\"SQB Aura W3: limit\\t\\t%\"PRIx64\"\",\n+\t\t\t (uint64_t)npa_rsp->aura.limit);\n+\t\tnix_dump(\"SQB Aura W3: fc_ena\\t\\t%d\",\n+\t\t\t npa_rsp->aura.fc_ena);\n+\t\tnix_dump(\"SQB Aura W4: fc_addr\\t\\t0x%\"PRIx64\"\\n\",\n+\t\t\t npa_rsp->aura.fc_addr);\n \t}\n \n fail:\n@@ -498,3 +534,278 @@ otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)\n \tnix_dump(\"W5: vtag0_ptr \\t%d\\t\\tvtag1_ptr \\t%d\\t\\tflow_key_alg \\t%d\",\n \t\t rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);\n }\n+\n+static uint8_t\n+prepare_nix_tm_reg_dump(uint16_t hw_lvl, uint16_t schq, uint16_t link,\n+\t\t\tuint64_t *reg, char regstr[][NIX_REG_NAME_SZ])\n+{\n+\tuint8_t k = 0;\n+\n+\tswitch (hw_lvl) {\n+\tcase NIX_TXSCH_LVL_SMQ:\n+\t\treg[k] = NIX_AF_SMQX_CFG(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_SMQ[%u]_CFG\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_PARENT\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_PIR\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_SHAPE\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_SW_XOFF\", schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\treg[k] = NIX_AF_TL4X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_PARENT\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SDP_LINK_CFG\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_PIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SHAPE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SW_XOFF\", schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\treg[k] = NIX_AF_TL3X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_PARENT\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG\", schq, link);\n+\n+\t\treg[k] = NIX_AF_TL3X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_PIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_SHAPE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_SW_XOFF\", schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\treg[k] = NIX_AF_TL2X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_PARENT\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG\", schq, link);\n+\n+\t\treg[k] = NIX_AF_TL2X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_PIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_SHAPE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_SW_XOFF\", schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL1:\n+\n+\t\treg[k] = NIX_AF_TL1X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_SW_XOFF\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_DROPPED_PACKETS\", schq);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (k > MAX_REGS_PER_MBOX_MSG) {\n+\t\tnix_dump(\"\\t!!!NIX TM Registers request overflow!!!\");\n+\t\treturn 0;\n+\t}\n+\treturn k;\n+}\n+\n+/* Dump TM hierarchy and registers */\n+void\n+otx2_nix_tm_dump(struct otx2_eth_dev *dev)\n+{\n+\tchar regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];\n+\tstruct otx2_nix_tm_node *tm_node, *root_node, *parent;\n+\tuint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];\n+\tstruct nix_txschq_config *req;\n+\tconst char *lvlstr, *parent_lvlstr;\n+\tstruct nix_txschq_config *rsp;\n+\tuint32_t schq, parent_schq;\n+\tint hw_lvl, j, k, rc;\n+\n+\tnix_dump(\"===TM hierarchy and registers dump of %s===\",\n+\t\t dev->eth_dev->data->name);\n+\n+\troot_node = NULL;\n+\n+\tfor (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++) {\n+\t\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n+\t\t\tif (tm_node->hw_lvl != hw_lvl)\n+\t\t\t\tcontinue;\n+\n+\t\t\tparent = tm_node->parent;\n+\t\t\tif (hw_lvl == NIX_TXSCH_LVL_CNT) {\n+\t\t\t\tlvlstr = \"SQ\";\n+\t\t\t\tschq = tm_node->id;\n+\t\t\t} else {\n+\t\t\t\tlvlstr = nix_hwlvl2str(tm_node->hw_lvl);\n+\t\t\t\tschq = tm_node->hw_id;\n+\t\t\t}\n+\n+\t\t\tif (parent) {\n+\t\t\t\tparent_schq = parent->hw_id;\n+\t\t\t\tparent_lvlstr =\n+\t\t\t\t\tnix_hwlvl2str(parent->hw_lvl);\n+\t\t\t} else if (tm_node->hw_lvl == NIX_TXSCH_LVL_TL1) {\n+\t\t\t\tparent_schq = otx2_nix_get_link(dev);\n+\t\t\t\tparent_lvlstr = \"LINK\";\n+\t\t\t} else {\n+\t\t\t\tparent_schq = tm_node->parent_hw_id;\n+\t\t\t\tparent_lvlstr =\n+\t\t\t\t\tnix_hwlvl2str(tm_node->hw_lvl + 1);\n+\t\t\t}\n+\n+\t\t\tnix_dump(\"%s_%d->%s_%d\", lvlstr, schq,\n+\t\t\t\t parent_lvlstr, parent_schq);\n+\n+\t\t\tif (!(tm_node->flags & NIX_TM_NODE_HWRES))\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Need to dump TL1 when root is TL2 */\n+\t\t\tif (tm_node->hw_lvl == dev->otx2_tm_root_lvl)\n+\t\t\t\troot_node = tm_node;\n+\n+\t\t\t/* Dump registers only when HWRES is present */\n+\t\t\tk = prepare_nix_tm_reg_dump(tm_node->hw_lvl, schq,\n+\t\t\t\t\t\t otx2_nix_get_link(dev), reg,\n+\t\t\t\t\t\t regstr);\n+\t\t\tif (!k)\n+\t\t\t\tcontinue;\n+\n+\t\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n+\t\t\treq->read = 1;\n+\t\t\treq->lvl = tm_node->hw_lvl;\n+\t\t\treq->num_regs = k;\n+\t\t\totx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n+\t\t\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n+\t\t\tif (!rc) {\n+\t\t\t\tfor (j = 0; j < k; j++)\n+\t\t\t\t\tnix_dump(\"\\t%s=0x%016\"PRIx64,\n+\t\t\t\t\t\t regstr[j], rsp->regval[j]);\n+\t\t\t} else {\n+\t\t\t\tnix_dump(\"\\t!!!Failed to dump registers!!!\");\n+\t\t\t}\n+\t\t}\n+\t\tnix_dump(\"\\n\");\n+\t}\n+\n+\t/* Dump TL1 node data when root level is TL2 */\n+\tif (root_node && root_node->hw_lvl == NIX_TXSCH_LVL_TL2) {\n+\t\tk = prepare_nix_tm_reg_dump(NIX_TXSCH_LVL_TL1,\n+\t\t\t\t\t root_node->parent_hw_id,\n+\t\t\t\t\t otx2_nix_get_link(dev),\n+\t\t\t\t\t reg, regstr);\n+\t\tif (!k)\n+\t\t\treturn;\n+\n+\n+\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n+\t\treq->read = 1;\n+\t\treq->lvl = NIX_TXSCH_LVL_TL1;\n+\t\treq->num_regs = k;\n+\t\totx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n+\t\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n+\t\tif (!rc) {\n+\t\t\tfor (j = 0; j < k; j++)\n+\t\t\t\tnix_dump(\"\\t%s=0x%016\"PRIx64,\n+\t\t\t\t\t regstr[j], rsp->regval[j]);\n+\t\t} else {\n+\t\t\tnix_dump(\"\\t!!!Failed to dump registers!!!\");\n+\t\t}\n+\t}\n+\n+\totx2_nix_queues_ctx_dump(dev->eth_dev);\n+}\ndiff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\nindex d8e54ee..c235c00 100644\n--- a/drivers/net/octeontx2/otx2_tm.c\n+++ b/drivers/net/octeontx2/otx2_tm.c\n@@ -28,8 +28,8 @@ uint64_t shaper2regval(struct shaper_params *shaper)\n \t\t(shaper->mantissa << 1);\n }\n \n-static int\n-nix_get_link(struct otx2_eth_dev *dev)\n+int\n+otx2_nix_get_link(struct otx2_eth_dev *dev)\n {\n \tint link = 13 /* SDP */;\n \tuint16_t lmac_chan;\n@@ -574,7 +574,7 @@ populate_tm_reg(struct otx2_eth_dev *dev,\n \t\tif (!otx2_dev_is_sdp(dev) &&\n \t\t dev->link_cfg_lvl == NIX_TXSCH_LVL_TL3) {\n \t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n-\t\t\t\t\t\tnix_get_link(dev));\n+\t\t\t\t\t\totx2_nix_get_link(dev));\n \t\t\tregval[k] = BIT_ULL(12) | nix_get_relchan(dev);\n \t\t\tk++;\n \t\t}\n@@ -594,7 +594,7 @@ populate_tm_reg(struct otx2_eth_dev *dev,\n \t\tif (!otx2_dev_is_sdp(dev) &&\n \t\t dev->link_cfg_lvl == NIX_TXSCH_LVL_TL2) {\n \t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n-\t\t\t\t\t\tnix_get_link(dev));\n+\t\t\t\t\t\totx2_nix_get_link(dev));\n \t\t\tregval[k] = BIT_ULL(12) | nix_get_relchan(dev);\n \t\t\tk++;\n \t\t}\n@@ -990,6 +990,7 @@ nix_txq_flush_sq_spin(struct otx2_eth_txq *txq)\n \n \treturn 0;\n exit:\n+\totx2_nix_tm_dump(dev);\n \treturn -EFAULT;\n }\n \ndiff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h\nindex 20e2069..d5d58ec 100644\n--- a/drivers/net/octeontx2/otx2_tm.h\n+++ b/drivers/net/octeontx2/otx2_tm.h\n@@ -23,6 +23,7 @@ int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,\n int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);\n int otx2_nix_sq_flush_post(void *_txq);\n int otx2_nix_sq_enable(void *_txq);\n+int otx2_nix_get_link(struct otx2_eth_dev *dev);\n int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);\n \n struct otx2_nix_tm_node {\n", "prefixes": [ "v3", "09/11" ] }