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{
    "id": 66585,
    "url": "http://patches.dpdk.org/api/patches/66585/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200312111907.31555-11-ndabilpuram@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200312111907.31555-11-ndabilpuram@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200312111907.31555-11-ndabilpuram@marvell.com",
    "date": "2020-03-12T11:19:06",
    "name": "[10/11] net/octeontx2: add tx queue ratelimit callback",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "f02be9e49024d132b607783e0951a693aec2aa18",
    "submitter": {
        "id": 1202,
        "url": "http://patches.dpdk.org/api/people/1202/?format=api",
        "name": "Nithin Dabilpuram",
        "email": "ndabilpuram@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patches.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200312111907.31555-11-ndabilpuram@marvell.com/mbox/",
    "series": [
        {
            "id": 8894,
            "url": "http://patches.dpdk.org/api/series/8894/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8894",
            "date": "2020-03-12T11:18:56",
            "name": "net/octeontx2: add traffic manager support",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/8894/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/66585/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/66585/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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            "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 0CE533F7041;\n Thu, 12 Mar 2020 04:19:35 -0700 (PDT)"
        ],
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        "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>",
        "CC": "Krzysztof Kanas <kkanas@marvell.com>, <dev@dpdk.org>",
        "Date": "Thu, 12 Mar 2020 16:49:06 +0530",
        "Message-ID": "<20200312111907.31555-11-ndabilpuram@marvell.com>",
        "X-Mailer": "git-send-email 2.8.4",
        "In-Reply-To": "<20200312111907.31555-1-ndabilpuram@marvell.com>",
        "References": "<20200312111907.31555-1-ndabilpuram@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572\n definitions=2020-03-12_03:2020-03-11,\n 2020-03-12 signatures=0",
        "Subject": "[dpdk-dev] [PATCH 10/11] net/octeontx2: add tx queue ratelimit\n\tcallback",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Krzysztof Kanas <kkanas@marvell.com>\n\nAdd Tx queue ratelimiting support. This support is mutually\nexclusive with TM support i.e when TM is configured, tx queue\nratelimiting config is no more valid.\n\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/octeontx2/otx2_ethdev.c |   1 +\n drivers/net/octeontx2/otx2_tm.c     | 241 +++++++++++++++++++++++++++++++++++-\n drivers/net/octeontx2/otx2_tm.h     |   3 +\n 3 files changed, 243 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 6896797..78b7f3a 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -2071,6 +2071,7 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.rx_descriptor_status     = otx2_nix_rx_descriptor_status,\n \t.tx_descriptor_status     = otx2_nix_tx_descriptor_status,\n \t.tx_done_cleanup          = otx2_nix_tx_done_cleanup,\n+\t.set_queue_rate_limit     = otx2_nix_tm_set_queue_rate_limit,\n \t.pool_ops_supported       = otx2_nix_pool_ops_supported,\n \t.filter_ctrl              = otx2_nix_dev_filter_ctrl,\n \t.get_module_info          = otx2_nix_get_module_info,\ndiff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\nindex 29c61de..bafb9aa 100644\n--- a/drivers/net/octeontx2/otx2_tm.c\n+++ b/drivers/net/octeontx2/otx2_tm.c\n@@ -2195,14 +2195,15 @@ nix_tm_hierarchy_commit(struct rte_eth_dev *eth_dev,\n \t}\n \n \t/* Delete default/ratelimit tree */\n-\tif (dev->tm_flags & (NIX_TM_DEFAULT_TREE)) {\n+\tif (dev->tm_flags & (NIX_TM_DEFAULT_TREE | NIX_TM_RATE_LIMIT_TREE)) {\n \t\trc = nix_tm_free_resources(dev, NIX_TM_NODE_USER, 0, false);\n \t\tif (rc) {\n \t\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n \t\t\terror->message = \"failed to free default resources\";\n \t\t\treturn rc;\n \t\t}\n-\t\tdev->tm_flags &= ~(NIX_TM_DEFAULT_TREE);\n+\t\tdev->tm_flags &= ~(NIX_TM_DEFAULT_TREE |\n+\t\t\t\t   NIX_TM_RATE_LIMIT_TREE);\n \t}\n \n \t/* Free up user alloc'ed resources */\n@@ -2663,6 +2664,242 @@ int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)\n \treturn 0;\n }\n \n+static int\n+nix_tm_prepare_rate_limited_tree(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint32_t def = eth_dev->data->nb_tx_queues;\n+\tstruct rte_tm_node_params params;\n+\tuint32_t leaf_parent, i, rc = 0;\n+\n+\tmemset(&params, 0, sizeof(params));\n+\n+\tif (nix_tm_have_tl1_access(dev)) {\n+\t\tdev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL1;\n+\t\trc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,\n+\t\t\t\t\tDEFAULT_RR_WEIGHT,\n+\t\t\t\t\tNIX_TXSCH_LVL_TL1,\n+\t\t\t\t\tOTX2_TM_LVL_ROOT, false, &params);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\trc = nix_tm_node_add_to_list(dev, def + 1, def, 0,\n+\t\t\t\t\tDEFAULT_RR_WEIGHT,\n+\t\t\t\t\tNIX_TXSCH_LVL_TL2,\n+\t\t\t\t\tOTX2_TM_LVL_SCH1, false, &params);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\trc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,\n+\t\t\t\t\tDEFAULT_RR_WEIGHT,\n+\t\t\t\t\tNIX_TXSCH_LVL_TL3,\n+\t\t\t\t\tOTX2_TM_LVL_SCH2, false, &params);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\trc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,\n+\t\t\t\t\tDEFAULT_RR_WEIGHT,\n+\t\t\t\t\tNIX_TXSCH_LVL_TL4,\n+\t\t\t\t\tOTX2_TM_LVL_SCH3, false, &params);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\tleaf_parent = def + 3;\n+\n+\t\t/* Add per queue SMQ nodes */\n+\t\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\t\trc = nix_tm_node_add_to_list(dev, leaf_parent + 1 + i,\n+\t\t\t\t\t\tleaf_parent,\n+\t\t\t\t\t\t0, DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t\tNIX_TXSCH_LVL_SMQ,\n+\t\t\t\t\t\tOTX2_TM_LVL_SCH4,\n+\t\t\t\t\t\tfalse, &params);\n+\t\t\tif (rc)\n+\t\t\t\tgoto error;\n+\t\t}\n+\n+\t\t/* Add leaf nodes */\n+\t\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\t\trc = nix_tm_node_add_to_list(dev, i,\n+\t\t\t\t\t\t     leaf_parent + 1 + i, 0,\n+\t\t\t\t\t\t     DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t\t     NIX_TXSCH_LVL_CNT,\n+\t\t\t\t\t\t     OTX2_TM_LVL_QUEUE,\n+\t\t\t\t\t\t     false, &params);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t\t}\n+\n+\t\treturn 0;\n+\t}\n+\n+\tdev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL2;\n+\trc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,\n+\t\t\t\tDEFAULT_RR_WEIGHT, NIX_TXSCH_LVL_TL2,\n+\t\t\t\tOTX2_TM_LVL_ROOT, false, &params);\n+\tif (rc)\n+\t\tgoto error;\n+\trc = nix_tm_node_add_to_list(dev, def + 1, def, 0,\n+\t\t\t\tDEFAULT_RR_WEIGHT, NIX_TXSCH_LVL_TL3,\n+\t\t\t\tOTX2_TM_LVL_SCH1, false, &params);\n+\tif (rc)\n+\t\tgoto error;\n+\trc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,\n+\t\t\t\t     DEFAULT_RR_WEIGHT, NIX_TXSCH_LVL_TL4,\n+\t\t\t\t     OTX2_TM_LVL_SCH2, false, &params);\n+\tif (rc)\n+\t\tgoto error;\n+\tleaf_parent = def + 2;\n+\n+\t/* Add per queue SMQ nodes */\n+\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\trc = nix_tm_node_add_to_list(dev, leaf_parent + 1 + i,\n+\t\t\t\t\t     leaf_parent,\n+\t\t\t\t\t     0, DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t     NIX_TXSCH_LVL_SMQ,\n+\t\t\t\t\t     OTX2_TM_LVL_SCH3,\n+\t\t\t\t\t     false, &params);\n+\t\tif (rc)\n+\t\t\tgoto error;\n+\t}\n+\n+\t/* Add leaf nodes */\n+\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\trc = nix_tm_node_add_to_list(dev, i, leaf_parent + 1 + i, 0,\n+\t\t\t\t\t     DEFAULT_RR_WEIGHT,\n+\t\t\t\t\t     NIX_TXSCH_LVL_CNT,\n+\t\t\t\t\t     OTX2_TM_LVL_SCH4,\n+\t\t\t\t\t     false, &params);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\t}\n+error:\n+\treturn rc;\n+}\n+\n+static int\n+otx2_nix_tm_rate_limit_mdq(struct rte_eth_dev *eth_dev,\n+\t\t\t   struct otx2_nix_tm_node *tm_node,\n+\t\t\t   uint64_t tx_rate)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_nix_tm_shaper_profile profile;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tvolatile uint64_t *reg, *regval;\n+\tstruct nix_txschq_config *req;\n+\tuint16_t flags;\n+\tuint8_t k = 0;\n+\tint rc;\n+\n+\tflags = tm_node->flags;\n+\n+\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\treq->lvl = NIX_TXSCH_LVL_MDQ;\n+\treg = req->reg;\n+\tregval = req->regval;\n+\n+\tif (tx_rate == 0) {\n+\t\tk += prepare_tm_sw_xoff(tm_node, true, &reg[k], &regval[k]);\n+\t\tflags &= ~NIX_TM_NODE_ENABLED;\n+\t\tgoto exit;\n+\t}\n+\n+\tif (!(flags & NIX_TM_NODE_ENABLED)) {\n+\t\tk += prepare_tm_sw_xoff(tm_node, false, &reg[k], &regval[k]);\n+\t\tflags |= NIX_TM_NODE_ENABLED;\n+\t}\n+\n+\t/* Use only PIR for rate limit */\n+\tmemset(&profile, 0, sizeof(profile));\n+\tprofile.params.peak.rate = tx_rate;\n+\t/* Minimum burst of ~4us Bytes of Tx */\n+\tprofile.params.peak.size = RTE_MAX(NIX_MAX_HW_FRS,\n+\t\t\t\t\t   (4ull * tx_rate) / (1E6 * 8));\n+\tif (!dev->tm_rate_min || dev->tm_rate_min > tx_rate)\n+\t\tdev->tm_rate_min = tx_rate;\n+\n+\tk += prepare_tm_shaper_reg(tm_node, &profile, &reg[k], &regval[k]);\n+exit:\n+\treq->num_regs = k;\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\ttm_node->flags = flags;\n+\treturn 0;\n+}\n+\n+int\n+otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,\n+\t\t\t\tuint16_t queue_idx, uint16_t tx_rate_mbps)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint64_t tx_rate = tx_rate_mbps * (uint64_t)1E6;\n+\tstruct otx2_nix_tm_node *tm_node;\n+\tint rc;\n+\n+\t/* Check for supported revisions */\n+\tif (otx2_dev_is_95xx_Ax(dev) ||\n+\t    otx2_dev_is_96xx_Ax(dev))\n+\t\treturn -EINVAL;\n+\n+\tif (queue_idx >= eth_dev->data->nb_tx_queues)\n+\t\treturn -EINVAL;\n+\n+\tif (!(dev->tm_flags & NIX_TM_DEFAULT_TREE) &&\n+\t    !(dev->tm_flags & NIX_TM_RATE_LIMIT_TREE))\n+\t\tgoto error;\n+\n+\tif ((dev->tm_flags & NIX_TM_DEFAULT_TREE) &&\n+\t    eth_dev->data->nb_tx_queues > 1) {\n+\t\t/* For TM topology change ethdev needs to be stopped */\n+\t\tif (eth_dev->data->dev_started)\n+\t\t\treturn -EBUSY;\n+\n+\t\t/*\n+\t\t * Disable xmit will be enabled when\n+\t\t * new topology is available.\n+\t\t */\n+\t\trc = nix_xmit_disable(eth_dev);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"failed to disable TX, rc=%d\", rc);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\trc = nix_tm_free_resources(dev, 0, 0, false);\n+\t\tif (rc < 0) {\n+\t\t\totx2_tm_dbg(\"failed to free default resources, rc %d\",\n+\t\t\t\t   rc);\n+\t\t\treturn -EIO;\n+\t\t}\n+\n+\t\trc = nix_tm_prepare_rate_limited_tree(eth_dev);\n+\t\tif (rc < 0) {\n+\t\t\totx2_tm_dbg(\"failed to prepare tm tree, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\trc = nix_tm_alloc_resources(eth_dev, true);\n+\t\tif (rc != 0) {\n+\t\t\totx2_tm_dbg(\"failed to allocate tm tree, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tdev->tm_flags &= ~NIX_TM_DEFAULT_TREE;\n+\t\tdev->tm_flags |= NIX_TM_RATE_LIMIT_TREE;\n+\t}\n+\n+\ttm_node = nix_tm_node_search(dev, queue_idx, false);\n+\n+\t/* check if we found a valid leaf node */\n+\tif (!tm_node ||\n+\t    !nix_tm_is_leaf(dev, tm_node->lvl) ||\n+\t    !tm_node->parent ||\n+\t    tm_node->parent->hw_id == UINT32_MAX)\n+\t\treturn -EIO;\n+\n+\treturn otx2_nix_tm_rate_limit_mdq(eth_dev, tm_node->parent, tx_rate);\n+error:\n+\totx2_tm_dbg(\"Unsupported TM tree 0x%0x\", dev->tm_flags);\n+\treturn -EINVAL;\n+}\n+\n int\n otx2_nix_tm_fini(struct rte_eth_dev *eth_dev)\n {\ndiff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h\nindex d5d58ec..7b1672e 100644\n--- a/drivers/net/octeontx2/otx2_tm.h\n+++ b/drivers/net/octeontx2/otx2_tm.h\n@@ -11,6 +11,7 @@\n \n #define NIX_TM_DEFAULT_TREE\tBIT_ULL(0)\n #define NIX_TM_COMMITTED\tBIT_ULL(1)\n+#define NIX_TM_RATE_LIMIT_TREE\tBIT_ULL(2)\n #define NIX_TM_TL1_NO_SP\tBIT_ULL(3)\n \n struct otx2_eth_dev;\n@@ -20,6 +21,8 @@ int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);\n int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);\n int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,\n \t\t\t      uint32_t *rr_quantum, uint16_t *smq);\n+int otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,\n+\t\t\t\t     uint16_t queue_idx, uint16_t tx_rate);\n int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);\n int otx2_nix_sq_flush_post(void *_txq);\n int otx2_nix_sq_enable(void *_txq);\n",
    "prefixes": [
        "10/11"
    ]
}