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GET /api/patches/66584/?format=api
{ "id": 66584, "url": "http://patches.dpdk.org/api/patches/66584/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200312111907.31555-10-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200312111907.31555-10-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200312111907.31555-10-ndabilpuram@marvell.com", "date": "2020-03-12T11:19:05", "name": "[09/11] net/octeontx2: add tm debug support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "17ff1004a54cbc2cd3c9fc3684f271e854206642", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200312111907.31555-10-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 8894, "url": "http://patches.dpdk.org/api/series/8894/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8894", "date": "2020-03-12T11:18:56", "name": "net/octeontx2: add traffic manager support", "version": 1, "mbox": "http://patches.dpdk.org/series/8894/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66584/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/66584/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0275AA056B;\n\tThu, 12 Mar 2020 12:21:39 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 039581C0C7;\n\tThu, 12 Mar 2020 12:19:40 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 78BB31C0BF\n for <dev@dpdk.org>; Thu, 12 Mar 2020 12:19:38 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 02CBFuN3017737 for <dev@dpdk.org>; Thu, 12 Mar 2020 04:19:38 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 2yqfggs6fx-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 12 Mar 2020 04:19:37 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Mar\n 2020 04:19:35 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n (10.93.176.81) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 12 Mar 2020 04:19:35 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id C7E1F3F703F;\n Thu, 12 Mar 2020 04:19:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0818; bh=8AMEf8gwJ79ho9n9uyoD/fbDg/TaEDNSfG8SLfzIQKU=;\n b=GoPNBNAkjCDDPl6R4Lv08AQsaJiCyxYywtHzcdWQGGWEUJmXglOcDwdzrVufg+er2yVx\n hklXynxPTAzP1CVKhx7pqIPsV8QPCJkwf6HMWkm/QAYmtO64jkRBUTLLMwP0v0IhamAE\n HIdyrIFGhK7vwdxtOk/s9cBk7gX6Vs1OL/yONxZ7E8vuiTO+9vknlH4qGd6J0ME1mQGn\n iQXUIvATeYpefwwca/wKNeHeEUNR/2K6NVvwn65gvmbuoC4Gt5l7fHBZyiKX91pSvZbm\n CU2fCTbc9nt9eFAWWrExpSZv5UN3KADEqcJSB1rbiADAkgrabfBIrLSvSURGKRvHjSaj 2g==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n <ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "Krzysztof Kanas <kkanas@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 12 Mar 2020 16:49:05 +0530", "Message-ID": "<20200312111907.31555-10-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20200312111907.31555-1-ndabilpuram@marvell.com>", "References": "<20200312111907.31555-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572\n definitions=2020-03-12_03:2020-03-11,\n 2020-03-12 signatures=0", "Subject": "[dpdk-dev] [PATCH 09/11] net/octeontx2: add tm debug support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add debug support to TM to dump configured topology\nand registers. Also enable debug dump when sq flush fails.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Krzysztof Kanas <kkanas@marvell.com>\n---\n drivers/net/octeontx2/otx2_ethdev.h | 1 +\n drivers/net/octeontx2/otx2_ethdev_debug.c | 274 ++++++++++++++++++++++++++++++\n drivers/net/octeontx2/otx2_tm.c | 9 +-\n drivers/net/octeontx2/otx2_tm.h | 1 +\n 4 files changed, 281 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 6679652..0ef90ce 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -459,6 +459,7 @@ int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,\n \t\t\t struct rte_dev_reg_info *regs);\n int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);\n void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);\n+void otx2_nix_tm_dump(struct otx2_eth_dev *dev);\n \n /* Stats */\n int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_debug.c b/drivers/net/octeontx2/otx2_ethdev_debug.c\nindex c8b4cd5..13e031e 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_debug.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_debug.c\n@@ -6,6 +6,7 @@\n \n #define nix_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n #define NIX_REG_INFO(reg) {reg, #reg}\n+#define NIX_REG_NAME_SZ 48\n \n struct nix_lf_reg_info {\n \tuint32_t offset;\n@@ -498,3 +499,276 @@ otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)\n \tnix_dump(\"W5: vtag0_ptr \\t%d\\t\\tvtag1_ptr \\t%d\\t\\tflow_key_alg \\t%d\",\n \t\t rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);\n }\n+\n+static uint8_t\n+prepare_nix_tm_reg_dump(uint16_t hw_lvl, uint16_t schq, uint16_t link,\n+\t\t\tuint64_t *reg, char regstr[][NIX_REG_NAME_SZ])\n+{\n+\tuint8_t k = 0;\n+\n+\tswitch (hw_lvl) {\n+\tcase NIX_TXSCH_LVL_SMQ:\n+\t\treg[k] = NIX_AF_SMQX_CFG(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_SMQ[%u]_CFG\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_PARENT\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_PIR\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_SHAPE\", schq);\n+\n+\t\treg[k] = NIX_AF_MDQX_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_MDQ[%u]_SW_XOFF\", schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL4:\n+\t\treg[k] = NIX_AF_TL4X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_PARENT\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SDP_LINK_CFG\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_PIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SHAPE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL4X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL4[%u]_SW_XOFF\", schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL3:\n+\t\treg[k] = NIX_AF_TL3X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_PARENT\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG\", schq, link);\n+\n+\t\treg[k] = NIX_AF_TL3X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_PIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_SHAPE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3[%u]_SW_XOFF\", schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL2:\n+\t\treg[k] = NIX_AF_TL2X_PARENT(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_PARENT\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG\", schq, link);\n+\n+\t\treg[k] = NIX_AF_TL2X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_PIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_PIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_SHAPE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_SHAPE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL2X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL2[%u]_SW_XOFF\", schq);\n+\t\tbreak;\n+\tcase NIX_TXSCH_LVL_TL1:\n+\n+\t\treg[k] = NIX_AF_TL1X_TOPOLOGY(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_TOPOLOGY\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_SCHEDULE(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_SCHEDULE\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_CIR(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_CIR\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_SW_XOFF(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_SW_XOFF\", schq);\n+\n+\t\treg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);\n+\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n+\t\t\t \"NIX_AF_TL1[%u]_DROPPED_PACKETS\", schq);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tif (k > MAX_REGS_PER_MBOX_MSG) {\n+\t\tnix_dump(\"\\t!!!NIX TM Registers request overflow!!!\");\n+\t\treturn 0;\n+\t}\n+\treturn k;\n+}\n+\n+/* Dump TM hierarchy and registers */\n+void\n+otx2_nix_tm_dump(struct otx2_eth_dev *dev)\n+{\n+\tchar regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];\n+\tstruct otx2_nix_tm_node *tm_node, *root_node, *parent;\n+\tuint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];\n+\tstruct nix_txschq_config *req;\n+\tconst char *lvlstr, *parent_lvlstr;\n+\tstruct nix_txschq_config *rsp;\n+\tuint32_t schq, parent_schq;\n+\tint hw_lvl, j, k, rc;\n+\n+\tnix_dump(\"===TM hierarchy and registers dump of %s===\",\n+\t\t dev->eth_dev->data->name);\n+\n+\troot_node = NULL;\n+\n+\tfor (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++) {\n+\t\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n+\t\t\tif (tm_node->hw_lvl != hw_lvl)\n+\t\t\t\tcontinue;\n+\n+\t\t\tparent = tm_node->parent;\n+\t\t\tif (hw_lvl == NIX_TXSCH_LVL_CNT) {\n+\t\t\t\tlvlstr = \"SQ\";\n+\t\t\t\tschq = tm_node->id;\n+\t\t\t} else {\n+\t\t\t\tlvlstr = nix_hwlvl2str(tm_node->hw_lvl);\n+\t\t\t\tschq = tm_node->hw_id;\n+\t\t\t}\n+\n+\t\t\tif (parent) {\n+\t\t\t\tparent_schq = parent->hw_id;\n+\t\t\t\tparent_lvlstr =\n+\t\t\t\t\tnix_hwlvl2str(parent->hw_lvl);\n+\t\t\t} else if (tm_node->hw_lvl == NIX_TXSCH_LVL_TL1) {\n+\t\t\t\tparent_schq = otx2_nix_get_link(dev);\n+\t\t\t\tparent_lvlstr = \"LINK\";\n+\t\t\t} else {\n+\t\t\t\tparent_schq = tm_node->parent_hw_id;\n+\t\t\t\tparent_lvlstr =\n+\t\t\t\t\tnix_hwlvl2str(tm_node->hw_lvl + 1);\n+\t\t\t}\n+\n+\t\t\tnix_dump(\"%s_%d->%s_%d\", lvlstr, schq,\n+\t\t\t\t parent_lvlstr, parent_schq);\n+\n+\t\t\tif (!(tm_node->flags & NIX_TM_NODE_HWRES))\n+\t\t\t\tcontinue;\n+\n+\t\t\t/* Need to dump TL1 when root is TL2 */\n+\t\t\tif (tm_node->hw_lvl == dev->otx2_tm_root_lvl)\n+\t\t\t\troot_node = tm_node;\n+\n+\t\t\t/* Dump registers only when HWRES is present */\n+\t\t\tk = prepare_nix_tm_reg_dump(tm_node->hw_lvl, schq,\n+\t\t\t\t\t\t otx2_nix_get_link(dev), reg,\n+\t\t\t\t\t\t regstr);\n+\t\t\tif (!k)\n+\t\t\t\tcontinue;\n+\n+\t\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n+\t\t\treq->read = 1;\n+\t\t\treq->lvl = tm_node->hw_lvl;\n+\t\t\treq->num_regs = k;\n+\t\t\totx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n+\t\t\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n+\t\t\tif (!rc) {\n+\t\t\t\tfor (j = 0; j < k; j++)\n+\t\t\t\t\tnix_dump(\"\\t%s=0x%016lx\",\n+\t\t\t\t\t\t regstr[j], rsp->regval[j]);\n+\t\t\t} else {\n+\t\t\t\tnix_dump(\"\\t!!!Failed to dump registers!!!\");\n+\t\t\t}\n+\t\t}\n+\t\tnix_dump(\"\\n\");\n+\t}\n+\n+\t/* Dump TL1 node data when root level is TL2 */\n+\tif (root_node && root_node->hw_lvl == NIX_TXSCH_LVL_TL2) {\n+\t\tk = prepare_nix_tm_reg_dump(NIX_TXSCH_LVL_TL1,\n+\t\t\t\t\t root_node->parent_hw_id,\n+\t\t\t\t\t otx2_nix_get_link(dev),\n+\t\t\t\t\t reg, regstr);\n+\t\tif (!k)\n+\t\t\treturn;\n+\n+\n+\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n+\t\treq->read = 1;\n+\t\treq->lvl = NIX_TXSCH_LVL_TL1;\n+\t\treq->num_regs = k;\n+\t\totx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n+\t\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n+\t\tif (!rc) {\n+\t\t\tfor (j = 0; j < k; j++)\n+\t\t\t\tnix_dump(\"\\t%s=0x%016lx\",\n+\t\t\t\t\t regstr[j], rsp->regval[j]);\n+\t\t} else {\n+\t\t\tnix_dump(\"\\t!!!Failed to dump registers!!!\");\n+\t\t}\n+\t}\n+}\ndiff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\nindex f84d166..29c61de 100644\n--- a/drivers/net/octeontx2/otx2_tm.c\n+++ b/drivers/net/octeontx2/otx2_tm.c\n@@ -28,8 +28,8 @@ uint64_t shaper2regval(struct shaper_params *shaper)\n \t\t(shaper->mantissa << 1);\n }\n \n-static int\n-nix_get_link(struct otx2_eth_dev *dev)\n+int\n+otx2_nix_get_link(struct otx2_eth_dev *dev)\n {\n \tint link = 13 /* SDP */;\n \tuint16_t lmac_chan;\n@@ -574,7 +574,7 @@ populate_tm_reg(struct otx2_eth_dev *dev,\n \t\tif (!otx2_dev_is_sdp(dev) &&\n \t\t dev->link_cfg_lvl == NIX_TXSCH_LVL_TL3) {\n \t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n-\t\t\t\t\t\tnix_get_link(dev));\n+\t\t\t\t\t\totx2_nix_get_link(dev));\n \t\t\tregval[k] = BIT_ULL(12) | nix_get_relchan(dev);\n \t\t\tk++;\n \t\t}\n@@ -594,7 +594,7 @@ populate_tm_reg(struct otx2_eth_dev *dev,\n \t\tif (!otx2_dev_is_sdp(dev) &&\n \t\t dev->link_cfg_lvl == NIX_TXSCH_LVL_TL2) {\n \t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n-\t\t\t\t\t\tnix_get_link(dev));\n+\t\t\t\t\t\totx2_nix_get_link(dev));\n \t\t\tregval[k] = BIT_ULL(12) | nix_get_relchan(dev);\n \t\t\tk++;\n \t\t}\n@@ -990,6 +990,7 @@ nix_txq_flush_sq_spin(struct otx2_eth_txq *txq)\n \n \treturn 0;\n exit:\n+\totx2_nix_tm_dump(dev);\n \treturn -EFAULT;\n }\n \ndiff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h\nindex 20e2069..d5d58ec 100644\n--- a/drivers/net/octeontx2/otx2_tm.h\n+++ b/drivers/net/octeontx2/otx2_tm.h\n@@ -23,6 +23,7 @@ int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,\n int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);\n int otx2_nix_sq_flush_post(void *_txq);\n int otx2_nix_sq_enable(void *_txq);\n+int otx2_nix_get_link(struct otx2_eth_dev *dev);\n int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);\n \n struct otx2_nix_tm_node {\n", "prefixes": [ "09/11" ] }