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GET /api/patches/66438/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 66438,
    "url": "http://patches.dpdk.org/api/patches/66438/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-22-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200309114357.31800-22-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200309114357.31800-22-qi.z.zhang@intel.com",
    "date": "2020-03-09T11:43:50",
    "name": "[21/28] net/ice/base: implement new sr read functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "acb55a858354c5b0bdf7ce29cb45e6f12c88cfd1",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 31221,
        "url": "http://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-22-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 8843,
            "url": "http://patches.dpdk.org/api/series/8843/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8843",
            "date": "2020-03-09T11:43:29",
            "name": "update ice base code",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/8843/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/66438/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/66438/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F396DA052E;\n\tMon,  9 Mar 2020 12:43:55 +0100 (CET)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BE9D31C1B2;\n\tMon,  9 Mar 2020 12:41:14 +0100 (CET)",
            "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id 4E3951C1A5\n for <dev@dpdk.org>; Mon,  9 Mar 2020 12:41:12 +0100 (CET)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 04:41:11 -0700",
            "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2020 04:41:10 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.70,533,1574150400\"; d=\"scan'208\";a=\"276483631\"",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com,\n\tbeilei.xing@intel.com",
        "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Mon,  9 Mar 2020 19:43:50 +0800",
        "Message-Id": "<20200309114357.31800-22-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.13.6",
        "In-Reply-To": "<20200309114357.31800-1-qi.z.zhang@intel.com>",
        "References": "<20200309114357.31800-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 21/28] net/ice/base: implement new sr read\n\tfunctions",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Remove the ice_read_sr_aq function and implement ice_read_sr_word_aq\ndirectly in terms of the new ice_read_flat_nvm function. This simplifies\nthe code by reducing a now unnecessary reading function.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_nvm.c | 84 +++++++-----------------------------------\n 1 file changed, 13 insertions(+), 71 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex a5b990ff8..b679f43d7 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -117,91 +117,33 @@ ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,\n }\n \n /**\n- * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.\n- * @hw: pointer to the HW structure\n- * @offset: offset in words from module start\n- * @words: number of words to access\n- */\n-static enum ice_status\n-ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)\n-{\n-\tif ((offset + words) > hw->nvm.sr_words) {\n-\t\tice_debug(hw, ICE_DBG_NVM,\n-\t\t\t  \"NVM error: offset beyond SR lmt.\\n\");\n-\t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\tif (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {\n-\t\t/* We can access only up to 4KB (one sector), in one AQ write */\n-\t\tice_debug(hw, ICE_DBG_NVM,\n-\t\t\t  \"NVM error: tried to access %d words, limit is %d.\\n\",\n-\t\t\t  words, ICE_SR_SECTOR_SIZE_IN_WORDS);\n-\t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\tif (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=\n-\t    (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {\n-\t\t/* A single access cannot spread over two sectors */\n-\t\tice_debug(hw, ICE_DBG_NVM,\n-\t\t\t  \"NVM error: cannot spread over two sectors.\\n\");\n-\t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\treturn ICE_SUCCESS;\n-}\n-\n-/**\n- * ice_read_sr_aq - Read Shadow RAM.\n- * @hw: pointer to the HW structure\n- * @offset: offset in words from module start\n- * @words: number of words to read\n- * @data: buffer for words reads from Shadow RAM\n- * @last_command: tells the AdminQ that this is the last command\n- *\n- * Reads 16-bit word buffers from the Shadow RAM using the admin command.\n- */\n-static enum ice_status\n-ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,\n-\t       bool last_command)\n-{\n-\tenum ice_status status;\n-\n-\tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n-\n-\tstatus = ice_check_sr_access_params(hw, offset, words);\n-\n-\t/* values in \"offset\" and \"words\" parameters are sized as words\n-\t * (16 bits) but ice_aq_read_nvm expects these values in bytes.\n-\t * So do this conversion while calling ice_aq_read_nvm.\n-\t */\n-\tif (!status)\n-\t\tstatus = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,\n-\t\t\t\t\t 2 * offset, 2 * words, data,\n-\t\t\t\t\t last_command, true, NULL);\n-\n-\treturn status;\n-}\n-\n-/**\n  * ice_read_sr_word_aq - Reads Shadow RAM via AQ\n  * @hw: pointer to the HW structure\n  * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n  * @data: word read from the Shadow RAM\n  *\n- * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.\n+ * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.\n  */\n static enum ice_status\n ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)\n {\n+\tu32 bytes = sizeof(u16);\n \tenum ice_status status;\n+\t__le16 data_local;\n \n \tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n \n-\tstatus = ice_read_sr_aq(hw, offset, 1, data, true);\n-\tif (!status)\n-\t\t*data = LE16_TO_CPU(*(_FORCE_ __le16 *)data);\n+\t/* Note that ice_read_flat_nvm checks if the read is past the Shadow\n+\t * RAM size, and ensures we don't read across a Shadow RAM sector\n+\t * boundary\n+\t */\n+\tstatus = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,\n+\t\t\t\t   (u8 *)&data_local, true);\n+\tif (status)\n+\t\treturn status;\n \n-\treturn status;\n+\t*data = LE16_TO_CPU(data_local);\n+\treturn ICE_SUCCESS;\n }\n \n /**\n",
    "prefixes": [
        "21/28"
    ]
}