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GET /api/patches/66437/?format=api
{ "id": 66437, "url": "http://patches.dpdk.org/api/patches/66437/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-21-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200309114357.31800-21-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200309114357.31800-21-qi.z.zhang@intel.com", "date": "2020-03-09T11:43:49", "name": "[20/28] net/ice/base: add macro specifying max NVM offset", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "55222cb3e8495171e2e2474c5bccd42065b4398b", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200309114357.31800-21-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 8843, "url": "http://patches.dpdk.org/api/series/8843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8843", "date": "2020-03-09T11:43:29", "name": "update ice base code", "version": 1, "mbox": "http://patches.dpdk.org/series/8843/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66437/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66437/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 52DA7A052E;\n\tMon, 9 Mar 2020 12:43:47 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6AC1E1C1AB;\n\tMon, 9 Mar 2020 12:41:13 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by dpdk.org (Postfix) with ESMTP id 4C0D01C1A3\n for <dev@dpdk.org>; Mon, 9 Mar 2020 12:41:10 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 09 Mar 2020 04:41:09 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2020 04:41:08 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,533,1574150400\"; d=\"scan'208\";a=\"276483627\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com,\n\tbeilei.xing@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 9 Mar 2020 19:43:49 +0800", "Message-Id": "<20200309114357.31800-21-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "References": "<20200309114357.31800-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 20/28] net/ice/base: add macro specifying max NVM\n\toffset", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The ice_aq_read_nvm function uses a somewhat weird construction for\nverifying that the incoming offset is valid. Replace this construction\nwith a simple greater-than expression, and define the maximum value\n(24bits) in the ice_adminq_cmd.h\n\nBy providing a macro, the check becomes more clear. Additionally the\nmaximum offset can be used in other locations.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 3 ++-\n drivers/net/ice/base/ice_nvm.c | 3 +--\n 2 files changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 9375d615e..3ab76a3fd 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1678,8 +1678,9 @@ struct ice_aqc_sff_eeprom {\n * NVM Shadow RAM Dump commands (direct 0x0707)\n */\n struct ice_aqc_nvm {\n+#define ICE_AQC_NVM_MAX_OFFSET\t\t0xFFFFFF\n \t__le16 offset_low;\n-\tu8 offset_high;\n+\tu8 offset_high; /* For Write Activate offset_high is used as flags2 */\n \tu8 cmd_flags;\n #define ICE_AQC_NVM_LAST_CMD\t\tBIT(0)\n #define ICE_AQC_NVM_PCIR_REQ\t\tBIT(0)\t/* Used by NVM Write reply */\ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex 80420afd3..a5b990ff8 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -29,8 +29,7 @@ ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,\n \n \tcmd = &desc.params.nvm;\n \n-\t/* In offset the highest byte must be zeroed. */\n-\tif (offset & 0xFF000000)\n+\tif (offset > ICE_AQC_NVM_MAX_OFFSET)\n \t\treturn ICE_ERR_PARAM;\n \n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);\n", "prefixes": [ "20/28" ] }