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GET /api/patches/66262/?format=api
{ "id": 66262, "url": "http://patches.dpdk.org/api/patches/66262/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1583346152-10186-14-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1583346152-10186-14-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1583346152-10186-14-git-send-email-nicolas.chautru@intel.com", "date": "2020-03-04T18:22:30", "name": "[v2,13/15] test-bbdev: add support for FPGA driver initialization", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ea993aac18d7aa61d00a2c364e03887205821402", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1583346152-10186-14-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 8783, "url": "http://patches.dpdk.org/api/series/8783/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8783", "date": "2020-03-04T18:22:17", "name": "bbdev new features", "version": 2, "mbox": "http://patches.dpdk.org/series/8783/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/66262/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/66262/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1EA66A0573;\n\tWed, 4 Mar 2020 19:25:09 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E252A1C0AC;\n\tWed, 4 Mar 2020 19:23:04 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id EB8A51BFC8\n for <dev@dpdk.org>; Wed, 4 Mar 2020 19:22:49 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 04 Mar 2020 10:22:44 -0800", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by fmsmga008.fm.intel.com with ESMTP; 04 Mar 2020 10:22:43 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,514,1574150400\"; d=\"scan'208\";a=\"234199031\"", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "thomas@monjalon.net,\n\takhil.goyal@nxp.com,\n\tdev@dpdk.org", "Cc": "ferruh.yigit@intel.com,\n\tNic Chautru <nicolas.chautru@intel.com>", "Date": "Wed, 4 Mar 2020 10:22:30 -0800", "Message-Id": "<1583346152-10186-14-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1583346152-10186-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1582778348-113547-15-git-send-email-nicolas.chautru@intel.com>\n <1583346152-10186-1-git-send-email-nicolas.chautru@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 13/15] test-bbdev: add support for FPGA driver\n\tinitialization", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nic Chautru <nicolas.chautru@intel.com>\n\nAdding capacity to initialize the device driver from\nthe test-bbdev environment for the new device\nFPGA for 5GNR FEC.\n\nSigned-off-by: Nic Chautru <nicolas.chautru@intel.com>\n---\n app/test-bbdev/Makefile | 3 +++\n app/test-bbdev/meson.build | 3 +++\n app/test-bbdev/test_bbdev_perf.c | 58 ++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 64 insertions(+)", "diff": "diff --git a/app/test-bbdev/Makefile b/app/test-bbdev/Makefile\nindex c53982f..e951302 100644\n--- a/app/test-bbdev/Makefile\n+++ b/app/test-bbdev/Makefile\n@@ -24,5 +24,8 @@ LDLIBS += -lm\n ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC),y)\n LDLIBS += -lrte_pmd_bbdev_fpga_lte_fec\n endif\n+ifeq ($(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC),y)\n+LDLIBS += -lrte_pmd_bbdev_fpga_5gnr_fec\n+endif\n \n include $(RTE_SDK)/mk/rte.app.mk\ndiff --git a/app/test-bbdev/meson.build b/app/test-bbdev/meson.build\nindex 4f53a2e..e57e019 100644\n--- a/app/test-bbdev/meson.build\n+++ b/app/test-bbdev/meson.build\n@@ -10,3 +10,6 @@ deps += ['bbdev', 'bus_vdev']\n if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC')\n \tdeps += ['pmd_bbdev_fpga_lte_fec']\n endif\n+if dpdk_conf.has('RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC')\n+\tdeps += ['pmd_bbdev_fpga_5gnr_fec']\n+endif\n\\ No newline at end of file\ndiff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c\nindex 1017b97..50ffee0 100644\n--- a/app/test-bbdev/test_bbdev_perf.c\n+++ b/app/test-bbdev/test_bbdev_perf.c\n@@ -39,6 +39,19 @@\n #define FLR_4G_TIMEOUT 610\n #endif\n \n+#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC\n+#include <fpga_5gnr_fec.h>\n+#define FPGA_5GNR_PF_DRIVER_NAME (\"intel_fpga_5gnr_fec_pf\")\n+#define FPGA_5GNR_VF_DRIVER_NAME (\"intel_fpga_5gnr_fec_vf\")\n+#define VF_UL_5G_QUEUE_VALUE 4\n+#define VF_DL_5G_QUEUE_VALUE 4\n+#define UL_5G_BANDWIDTH 3\n+#define DL_5G_BANDWIDTH 3\n+#define UL_5G_LOAD_BALANCE 128\n+#define DL_5G_LOAD_BALANCE 128\n+#define FLR_5G_TIMEOUT 610\n+#endif\n+\n #define OPS_CACHE_SIZE 256U\n #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */\n \n@@ -587,6 +600,51 @@ typedef int (test_case_function)(struct active_device *ad,\n \t\t\t\tinfo->dev_name);\n \t}\n #endif\n+#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC\n+\tif ((get_init_device() == true) &&\n+\t\t(!strcmp(info->drv.driver_name, FPGA_5GNR_PF_DRIVER_NAME))) {\n+\t\tstruct fpga_5gnr_fec_conf conf;\n+\t\tunsigned int i;\n+\n+\t\tprintf(\"Configure FPGA 5GNR FEC Driver %s with default values\\n\",\n+\t\t\t\tinfo->drv.driver_name);\n+\n+\t\t/* clear default configuration before initialization */\n+\t\tmemset(&conf, 0, sizeof(struct fpga_5gnr_fec_conf));\n+\n+\t\t/* Set PF mode :\n+\t\t * true if PF is used for data plane\n+\t\t * false for VFs\n+\t\t */\n+\t\tconf.pf_mode_en = true;\n+\n+\t\tfor (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {\n+\t\t\t/* Number of UL queues per VF (fpga supports 8 VFs) */\n+\t\t\tconf.vf_ul_queues_number[i] = VF_UL_5G_QUEUE_VALUE;\n+\t\t\t/* Number of DL queues per VF (fpga supports 8 VFs) */\n+\t\t\tconf.vf_dl_queues_number[i] = VF_DL_5G_QUEUE_VALUE;\n+\t\t}\n+\n+\t\t/* UL bandwidth. Needed for schedule algorithm */\n+\t\tconf.ul_bandwidth = UL_5G_BANDWIDTH;\n+\t\t/* DL bandwidth */\n+\t\tconf.dl_bandwidth = DL_5G_BANDWIDTH;\n+\n+\t\t/* UL & DL load Balance Factor to 64 */\n+\t\tconf.ul_load_balance = UL_5G_LOAD_BALANCE;\n+\t\tconf.dl_load_balance = DL_5G_LOAD_BALANCE;\n+\n+\t\t/**< FLR timeout value */\n+\t\tconf.flr_time_out = FLR_5G_TIMEOUT;\n+\n+\t\t/* setup FPGA PF with configuration information */\n+\t\tret = fpga_5gnr_fec_configure(info->dev_name, &conf);\n+\t\tTEST_ASSERT_SUCCESS(ret,\n+\t\t\t\t\"Failed to configure 5G FPGA PF for bbdev %s\",\n+\t\t\t\tinfo->dev_name);\n+\t}\n+#endif\n+\n \tnb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues);\n \tnb_queues = RTE_MIN(nb_queues, (unsigned int) MAX_QUEUES);\n \n", "prefixes": [ "v2", "13/15" ] }