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GET /api/patches/64954/?format=api
{ "id": 64954, "url": "http://patches.dpdk.org/api/patches/64954/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-16-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1579539790-3882-16-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1579539790-3882-16-git-send-email-matan@mellanox.com", "date": "2020-01-20T17:02:47", "name": "[v1,15/38] common/mlx5: add DevX command to create CQ", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "3e12906f08acdc144d565f8a2f9380fec8e91e6c", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1579539790-3882-16-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 8223, "url": "http://patches.dpdk.org/api/series/8223/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8223", "date": "2020-01-20T17:02:37", "name": "Introduce mlx5 vDPA driver", "version": 1, "mbox": "http://patches.dpdk.org/series/8223/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64954/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/64954/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D164EA0526;\n\tMon, 20 Jan 2020 18:06:16 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DBAF21C010;\n\tMon, 20 Jan 2020 18:03:47 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 412851BF9D\n for <dev@dpdk.org>; Mon, 20 Jan 2020 18:03:14 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n asafp@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 20 Jan 2020 19:03:13 +0200", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n [10.210.16.112])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 00KH3BGY024424;\n Mon, 20 Jan 2020 19:03:13 +0200" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "dev@dpdk.org", "Cc": "Maxime Coquelin <maxime.coquelin@redhat.com>,\n Thomas Monjalon <thomas@monjalon.net>", "Date": "Mon, 20 Jan 2020 17:02:47 +0000", "Message-Id": "<1579539790-3882-16-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "References": "<1579539790-3882-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v1 15/38] common/mlx5: add DevX command to create\n\tCQ", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "HW implements completion queues(CQ) used to post completion reports upon\ncompletion of work request.\n\nUsed for Rx and Tx datapath.\n\nAdd DevX command to create a CQ.\n\nSigned-off-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 57 ++++++++++++++++++++\n drivers/common/mlx5/mlx5_devx_cmds.h | 19 +++++++\n drivers/common/mlx5/mlx5_prm.h | 71 +++++++++++++++++++++++++\n drivers/common/mlx5/rte_common_mlx5_version.map | 1 +\n 4 files changed, 148 insertions(+)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex aa2feeb..ef7d70c 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1091,3 +1091,60 @@ struct mlx5_devx_obj *\n #endif\n \treturn -ret;\n }\n+\n+/* \n+ * Create CQ using DevX API.\n+ *\n+ * @param[in] ctx\n+ * ibv_context returned from mlx5dv_open_device.\n+ * @param [in] attr\n+ * Pointer to CQ attributes structure.\n+ *\n+ * @return\n+ * The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_cq(struct ibv_context *ctx, struct mlx5_devx_cq_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};\n+\tstruct mlx5_devx_obj *cq_obj = rte_zmalloc(__func__, sizeof(*cq_obj),\n+\t\t\t\t\t\t 0);\n+\tvoid *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);\n+\n+\tif (!cq_obj) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate CQ object memory.\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);\n+\tif (attr->db_umem_valid) {\n+\t\tMLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);\n+\t\tMLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);\n+\t\tMLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);\n+\t} else {\n+\t\tMLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);\n+\t}\n+\tMLX5_SET(cqc, cqctx, cc, attr->use_first_only);\n+\tMLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);\n+\tMLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);\n+\tMLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size);\n+\tMLX5_SET(cqc, cqctx, c_eqn, attr->eqn);\n+\tMLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);\n+\tif (attr->q_umem_valid) {\n+\t\tMLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);\n+\t\tMLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);\n+\t\tMLX5_SET64(create_cq_in, in, cq_umem_offset,\n+\t\t\t attr->q_umem_offset);\n+\t}\n+\tcq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,\n+\t\t\t\t\t\t sizeof(out));\n+\tif (!cq_obj->obj) {\n+\t\trte_errno = errno;\n+\t\tDRV_LOG(ERR, \"Failed to create CQ using DevX errno=%d.\", errno);\n+\t\trte_free(cq_obj);\n+\t\treturn NULL;\n+\t}\n+\tcq_obj->id = MLX5_GET(create_cq_out, out, cqn);\n+\treturn cq_obj;\n+}\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex ceeca64..7b50861 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -224,6 +224,23 @@ struct mlx5_devx_modify_sq_attr {\n };\n \n \n+/* CQ attributes structure, used by CQ operations. */\n+struct mlx5_devx_cq_attr {\n+\tuint32_t q_umem_valid:1;\n+\tuint32_t db_umem_valid:1;\n+\tuint32_t use_first_only:1;\n+\tuint32_t overrun_ignore:1;\n+\tuint32_t log_cq_size:5;\n+\tuint32_t log_page_size:5;\n+\tuint32_t uar_page_id;\n+\tuint32_t q_umem_id;\n+\tuint64_t q_umem_offset;\n+\tuint32_t db_umem_id;\n+\tuint64_t db_umem_offset;\n+\tuint32_t eqn;\n+\tuint64_t db_addr;\n+};\n+\n /* mlx5_devx_cmds.c */\n \n struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,\n@@ -260,4 +277,6 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(struct ibv_context *ctx,\n struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);\n int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,\n \t\t\t FILE *file);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(struct ibv_context *ctx,\n+\t\t\t\t\t struct mlx5_devx_cq_attr *attr);\n #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 058bd8c..0206a8e 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -710,6 +710,7 @@ enum {\n enum {\n \tMLX5_CMD_OP_QUERY_HCA_CAP = 0x100,\n \tMLX5_CMD_OP_CREATE_MKEY = 0x200,\n+\tMLX5_CMD_OP_CREATE_CQ = 0x400,\n \tMLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,\n \tMLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,\n \tMLX5_CMD_OP_CREATE_TIR = 0x900,\n@@ -1844,6 +1845,76 @@ struct mlx5_ifc_flow_meter_parameters_bits {\n \tu8 reserved_at_8[0x60];\t\t// 14h-1Ch\n };\n \n+struct mlx5_ifc_cqc_bits {\n+\tu8 status[0x4];\n+\tu8 as_notify[0x1];\n+\tu8 initiator_src_dct[0x1];\n+\tu8 dbr_umem_valid[0x1];\n+\tu8 reserved_at_7[0x1];\n+\tu8 cqe_sz[0x3];\n+\tu8 cc[0x1];\n+\tu8 reserved_at_c[0x1];\n+\tu8 scqe_break_moderation_en[0x1];\n+\tu8 oi[0x1];\n+\tu8 cq_period_mode[0x2];\n+\tu8 cqe_comp_en[0x1];\n+\tu8 mini_cqe_res_format[0x2];\n+\tu8 st[0x4];\n+\tu8 reserved_at_18[0x8];\n+\tu8 dbr_umem_id[0x20];\n+\tu8 reserved_at_40[0x14];\n+\tu8 page_offset[0x6];\n+\tu8 reserved_at_5a[0x6];\n+\tu8 reserved_at_60[0x3];\n+\tu8 log_cq_size[0x5];\n+\tu8 uar_page[0x18];\n+\tu8 reserved_at_80[0x4];\n+\tu8 cq_period[0xc];\n+\tu8 cq_max_count[0x10];\n+\tu8 reserved_at_a0[0x18];\n+\tu8 c_eqn[0x8];\n+\tu8 reserved_at_c0[0x3];\n+\tu8 log_page_size[0x5];\n+\tu8 reserved_at_c8[0x18];\n+\tu8 reserved_at_e0[0x20];\n+\tu8 reserved_at_100[0x8];\n+\tu8 last_notified_index[0x18];\n+\tu8 reserved_at_120[0x8];\n+\tu8 last_solicit_index[0x18];\n+\tu8 reserved_at_140[0x8];\n+\tu8 consumer_counter[0x18];\n+\tu8 reserved_at_160[0x8];\n+\tu8 producer_counter[0x18];\n+\tu8 local_partition_id[0xc];\n+\tu8 process_id[0x14];\n+\tu8 reserved_at_1A0[0x20];\n+\tu8 dbr_addr[0x40];\n+};\n+\n+struct mlx5_ifc_create_cq_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 cqn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_create_cq_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x40];\n+\tstruct mlx5_ifc_cqc_bits cq_context;\n+\tu8 cq_umem_offset[0x40];\n+\tu8 cq_umem_id[0x20];\n+\tu8 cq_umem_valid[0x1];\n+\tu8 reserved_at_2e1[0x1f];\n+\tu8 reserved_at_300[0x580];\n+\tu8 pas[];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \ndiff --git a/drivers/common/mlx5/rte_common_mlx5_version.map b/drivers/common/mlx5/rte_common_mlx5_version.map\nindex 0c01172..c6a203d 100644\n--- a/drivers/common/mlx5/rte_common_mlx5_version.map\n+++ b/drivers/common/mlx5/rte_common_mlx5_version.map\n@@ -1,6 +1,7 @@\n DPDK_20.02 {\n \tglobal:\n \n+\tmlx5_devx_cmd_create_cq;\n \tmlx5_devx_cmd_create_rq;\n \tmlx5_devx_cmd_create_rqt;\n \tmlx5_devx_cmd_create_sq;\n", "prefixes": [ "v1", "15/38" ] }