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GET /api/patches/64687/?format=api
{ "id": 64687, "url": "http://patches.dpdk.org/api/patches/64687/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200115005028.21026-5-haiyue.wang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200115005028.21026-5-haiyue.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200115005028.21026-5-haiyue.wang@intel.com", "date": "2020-01-15T00:50:28", "name": "[v3,4/4] net/ice/base: osdep.h clean up", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d7041165ac5d22ab3383333fdccd96e35aa7abfe", "submitter": { "id": 1044, "url": "http://patches.dpdk.org/api/people/1044/?format=api", "name": "Wang, Haiyue", "email": "haiyue.wang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200115005028.21026-5-haiyue.wang@intel.com/mbox/", "series": [ { "id": 8127, "url": "http://patches.dpdk.org/api/series/8127/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8127", "date": "2020-01-15T00:50:24", "name": "Intel iavf and ice PMDs clean up", "version": 3, "mbox": "http://patches.dpdk.org/series/8127/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64687/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/64687/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B44A5A04FD;\n\tWed, 15 Jan 2020 01:58:00 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 2A20D1C123;\n\tWed, 15 Jan 2020 01:57:39 +0100 (CET)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by dpdk.org (Postfix) with ESMTP id 4884B1C0D5\n for <dev@dpdk.org>; Wed, 15 Jan 2020 01:57:31 +0100 (CET)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 14 Jan 2020 16:57:30 -0800", "from npg-dpdk-haiyue-1.sh.intel.com ([10.67.119.213])\n by fmsmga006.fm.intel.com with ESMTP; 14 Jan 2020 16:57:29 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.70,320,1574150400\"; d=\"scan'208\";a=\"424844024\"", "From": "Haiyue Wang <haiyue.wang@intel.com>", "To": "dev@dpdk.org, xiaolong.ye@intel.com, qi.z.zhang@intel.com,\n qiming.yang@intel.com", "Cc": "Haiyue Wang <haiyue.wang@intel.com>", "Date": "Wed, 15 Jan 2020 08:50:28 +0800", "Message-Id": "<20200115005028.21026-5-haiyue.wang@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200115005028.21026-1-haiyue.wang@intel.com>", "References": "<20200115005028.21026-1-haiyue.wang@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 4/4] net/ice/base: osdep.h clean up", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Remove the unused definitions, rewrite the IO data read/write helpers,\nand put the common definitions related to RTE defines under the macro\n__INTEL_NET_BASE_OSDEP__, so it works like OS(RTE) dependency.\n\nSigned-off-by: Haiyue Wang <haiyue.wang@intel.com>\n---\n drivers/net/ice/base/ice_osdep.h | 132 ++++++++++++++++---------------\n 1 file changed, 67 insertions(+), 65 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h\nindex 27c1830c5..45b9f3617 100644\n--- a/drivers/net/ice/base/ice_osdep.h\n+++ b/drivers/net/ice/base/ice_osdep.h\n@@ -26,6 +26,9 @@\n \n #include \"../ice_logs.h\"\n \n+#ifndef __INTEL_NET_BASE_OSDEP__\n+#define __INTEL_NET_BASE_OSDEP__\n+\n #define INLINE inline\n #define STATIC static\n \n@@ -38,17 +41,6 @@ typedef int32_t s32;\n typedef uint64_t u64;\n typedef uint64_t s64;\n \n-#define __iomem\n-#define hw_dbg(hw, S, A...) do {} while (0)\n-#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))\n-#define lower_32_bits(n) ((u32)(n))\n-#define low_16_bits(x) ((x) & 0xFFFF)\n-#define high_16_bits(x) (((x) & 0xFFFF0000) >> 16)\n-\n-#ifndef ETH_ADDR_LEN\n-#define ETH_ADDR_LEN 6\n-#endif\n-\n #ifndef __le16\n #define __le16 uint16_t\n #endif\n@@ -68,6 +60,65 @@ typedef uint64_t s64;\n #define __be64 uint64_t\n #endif\n \n+#define min(a, b) RTE_MIN(a, b)\n+#define max(a, b) RTE_MAX(a, b)\n+\n+#define FIELD_SIZEOF(t, f) RTE_SIZEOF_FIELD(t, f)\n+#define ARRAY_SIZE(arr) RTE_DIM(arr)\n+\n+#define CPU_TO_LE16(o) rte_cpu_to_le_16(o)\n+#define CPU_TO_LE32(s) rte_cpu_to_le_32(s)\n+#define CPU_TO_LE64(h) rte_cpu_to_le_64(h)\n+#define LE16_TO_CPU(a) rte_le_to_cpu_16(a)\n+#define LE32_TO_CPU(c) rte_le_to_cpu_32(c)\n+#define LE64_TO_CPU(k) rte_le_to_cpu_64(k)\n+\n+#define CPU_TO_BE16(o) rte_cpu_to_be_16(o)\n+#define CPU_TO_BE32(o) rte_cpu_to_be_32(o)\n+#define CPU_TO_BE64(o) rte_cpu_to_be_64(o)\n+\n+#define NTOHS(a) rte_be_to_cpu_16(a)\n+#define NTOHL(a) rte_be_to_cpu_32(a)\n+#define HTONS(a) rte_cpu_to_be_16(a)\n+#define HTONL(a) rte_cpu_to_be_32(a)\n+\n+static __rte_always_inline uint32_t\n+readl(volatile void *addr)\n+{\n+\treturn rte_le_to_cpu_32(rte_read32(addr));\n+}\n+\n+static __rte_always_inline void\n+writel(uint32_t value, volatile void *addr)\n+{\n+\trte_write32(rte_cpu_to_le_32(value), addr);\n+}\n+\n+static __rte_always_inline void\n+writel_relaxed(uint32_t value, volatile void *addr)\n+{\n+\trte_write32_relaxed(rte_cpu_to_le_32(value), addr);\n+}\n+\n+static __rte_always_inline uint64_t\n+readq(volatile void *addr)\n+{\n+\treturn rte_le_to_cpu_64(rte_read64(addr));\n+}\n+\n+static __rte_always_inline void\n+writeq(uint64_t value, volatile void *addr)\n+{\n+\trte_write64(rte_cpu_to_le_64(value), addr);\n+}\n+\n+#define wr32(a, reg, value) writel((value), (a)->hw_addr + (reg))\n+#define rd32(a, reg) readl((a)->hw_addr + (reg))\n+#define wr64(a, reg, value) writeq((value), (a)->hw_addr + (reg))\n+#define rd64(a, reg) readq((a)->hw_addr + (reg))\n+\n+#endif /* __INTEL_NET_BASE_OSDEP__ */\n+\n #ifndef __always_unused\n #define __always_unused __attribute__((unused))\n #endif\n@@ -82,21 +133,8 @@ typedef uint64_t s64;\n #define BIT_ULL(a) (1ULL << (a))\n #endif\n \n-#define FALSE 0\n-#define TRUE 1\n-#define false 0\n-#define true 1\n-\n-#define min(a, b) RTE_MIN(a, b)\n-#define max(a, b) RTE_MAX(a, b)\n-\n-#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0]))\n-#define FIELD_SIZEOF(t, f) (sizeof(((t *)0)->f))\n #define MAKEMASK(m, s) ((m) << (s))\n \n-#define DEBUGOUT(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)\n-#define DEBUGFUNC(F) PMD_DRV_LOG_RAW(DEBUG, F)\n-\n #define ice_debug(h, m, s, ...)\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n \tif (((m) & (h)->debug_mask))\t\t\t\t\\\n@@ -123,37 +161,16 @@ do {\t\t\t\t\t\t\t\t\t\\\n #define SNPRINTF ice_snprintf\n #endif\n \n-#define ICE_PCI_REG(reg) rte_read32(reg)\n-#define ICE_PCI_REG_ADDR(a, reg) \\\n-\t((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))\n-#define ICE_PCI_REG64(reg) rte_read64(reg)\n-#define ICE_PCI_REG_ADDR64(a, reg) \\\n-\t((volatile uint64_t *)((char *)(a)->hw_addr + (reg)))\n-static inline uint32_t ice_read_addr(volatile void *addr)\n-{\n-\treturn rte_le_to_cpu_32(ICE_PCI_REG(addr));\n-}\n-\n-static inline uint64_t ice_read_addr64(volatile void *addr)\n-{\n-\treturn rte_le_to_cpu_64(ICE_PCI_REG64(addr));\n-}\n+#define ICE_PCI_REG_WRITE(reg, value) writel(value, reg)\n \n-#define ICE_PCI_REG_WRITE(reg, value) \\\n-\trte_write32((rte_cpu_to_le_32(value)), reg)\n+#define ICE_READ_REG(hw, reg) rd32(hw, reg)\n+#define ICE_WRITE_REG(hw, reg, value) wr32(hw, reg, value)\n \n #define ice_flush(a) ICE_READ_REG((a), GLGEN_STAT)\n #define icevf_flush(a) ICE_READ_REG((a), VFGEN_RSTAT)\n-#define ICE_READ_REG(hw, reg) ice_read_addr(ICE_PCI_REG_ADDR((hw), (reg)))\n-#define ICE_WRITE_REG(hw, reg, value) \\\n-\tICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((hw), (reg)), (value))\n-\n-#define rd32(a, reg) ice_read_addr(ICE_PCI_REG_ADDR((a), (reg)))\n-#define wr32(a, reg, value) \\\n-\tICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((a), (reg)), (value))\n-#define flush(a) ice_read_addr(ICE_PCI_REG_ADDR((a), (GLGEN_STAT)))\n+\n+#define flush(a) ICE_READ_REG((a), GLGEN_STAT)\n #define div64_long(n, d) ((n) / (d))\n-#define rd64(a, reg) ice_read_addr64(ICE_PCI_REG_ADDR64((a), (reg)))\n \n #define BITS_PER_BYTE 8\n \n@@ -178,21 +195,6 @@ struct ice_virt_mem {\n #define ice_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))\n #define ice_memdup(a, b, c, d) rte_memcpy(ice_malloc(a, c), b, c)\n \n-#define CPU_TO_BE16(o) rte_cpu_to_be_16(o)\n-#define CPU_TO_BE32(o) rte_cpu_to_be_32(o)\n-#define CPU_TO_BE64(o) rte_cpu_to_be_64(o)\n-#define CPU_TO_LE16(o) rte_cpu_to_le_16(o)\n-#define CPU_TO_LE32(s) rte_cpu_to_le_32(s)\n-#define CPU_TO_LE64(h) rte_cpu_to_le_64(h)\n-#define LE16_TO_CPU(a) rte_le_to_cpu_16(a)\n-#define LE32_TO_CPU(c) rte_le_to_cpu_32(c)\n-#define LE64_TO_CPU(k) rte_le_to_cpu_64(k)\n-\n-#define NTOHS(a) rte_be_to_cpu_16(a)\n-#define NTOHL(a) rte_be_to_cpu_32(a)\n-#define HTONS(a) rte_cpu_to_be_16(a)\n-#define HTONL(a) rte_cpu_to_be_32(a)\n-\n /* SW spinlock */\n struct ice_lock {\n \trte_spinlock_t spinlock;\n", "prefixes": [ "v3", "4/4" ] }