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Update a patch.
GET /api/patches/64492/?format=api
{ "id": 64492, "url": "http://patches.dpdk.org/api/patches/64492/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200113023949.26718-29-xiaolong.ye@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200113023949.26718-29-xiaolong.ye@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200113023949.26718-29-xiaolong.ye@intel.com", "date": "2020-01-13T02:39:40", "name": "[v4,28/36] net/i40e/base: add Flow Director defines", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6abe1b46c692d2e46162dbe8e333ff985ce350ea", "submitter": { "id": 1120, "url": "http://patches.dpdk.org/api/people/1120/?format=api", "name": "Xiaolong Ye", "email": "xiaolong.ye@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200113023949.26718-29-xiaolong.ye@intel.com/mbox/", "series": [ { "id": 8064, "url": "http://patches.dpdk.org/api/series/8064/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8064", "date": "2020-01-13T02:39:12", "name": "update for i40e base code", "version": 4, "mbox": "http://patches.dpdk.org/series/8064/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64492/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/64492/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CB59BA04F0;\n\tMon, 13 Jan 2020 03:51:11 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CB91D1D636;\n\tMon, 13 Jan 2020 03:48:06 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by dpdk.org (Postfix) with ESMTP id 2A5371D5D5\n for <dev@dpdk.org>; Mon, 13 Jan 2020 03:47:37 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 12 Jan 2020 18:47:36 -0800", "from dpdk_yexl_af_xdp.sh.intel.com ([10.67.119.206])\n by FMSMGA003.fm.intel.com with ESMTP; 12 Jan 2020 18:47:35 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.69,427,1571727600\"; d=\"scan'208\";a=\"272916408\"", "From": "Xiaolong Ye <xiaolong.ye@intel.com>", "To": "Beilei Xing <beilei.xing@intel.com>,\n\tQi Zhang <qi.z.zhang@intel.com>", "Cc": "dev@dpdk.org, Xiaolong Ye <xiaolong.ye@intel.com>,\n Doug Dziggel <douglas.a.dziggel@intel.com>", "Date": "Mon, 13 Jan 2020 10:39:40 +0800", "Message-Id": "<20200113023949.26718-29-xiaolong.ye@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20200113023949.26718-1-xiaolong.ye@intel.com>", "References": "<20191202074935.97629-1-xiaolong.ye@intel.com>\n <20200113023949.26718-1-xiaolong.ye@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 28/36] net/i40e/base: add Flow Director defines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add defines for creating Flow Director flows as defined in datasheet\nsection 7.1.5.4 for field vectors.\n\nSigned-off-by: Doug Dziggel <douglas.a.dziggel@intel.com>\nSigned-off-by: Xiaolong Ye <xiaolong.ye@intel.com>\n---\n drivers/net/i40e/base/i40e_register.h | 81 +++++++++++++++++++++++++++\n 1 file changed, 81 insertions(+)", "diff": "diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h\nindex 6804aba51..3a8c0ccd1 100644\n--- a/drivers/net/i40e/base/i40e_register.h\n+++ b/drivers/net/i40e/base/i40e_register.h\n@@ -5287,6 +5287,87 @@\n #define I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT 0\n #define I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT)\n #endif /* PF_DRIVER */\n+/* Flow Director */\n+#define I40E_REG_INSET_L2_DMAC_SHIFT 60\n+#define I40E_REG_INSET_L2_DMAC_MASK I40E_MASK(0xEULL, I40E_REG_INSET_L2_DMAC_SHIFT)\n+#define I40E_REG_INSET_L2_SMAC_SHIFT 56\n+#define I40E_REG_INSET_L2_SMAC_MASK I40E_MASK(0x1CULL, I40E_REG_INSET_L2_SMAC_SHIFT)\n+#define I40E_REG_INSET_L2_OUTER_VLAN_SHIFT 26\n+#define I40E_REG_INSET_L2_OUTER_VLAN_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L2_OUTER_VLAN_SHIFT)\n+#define I40E_REG_INSET_L2_INNER_VLAN_SHIFT 55\n+#define I40E_REG_INSET_L2_INNER_VLAN_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L2_INNER_VLAN_SHIFT)\n+#define I40E_REG_INSET_TUNNEL_VLAN_SHIFT 56\n+#define I40E_REG_INSET_TUNNEL_VLAN_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_TUNNEL_VLAN_SHIFT)\n+#define I40E_REG_INSET_L3_SRC_IP4_SHIFT 47\n+#define I40E_REG_INSET_L3_SRC_IP4_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_L3_SRC_IP4_SHIFT)\n+#define I40E_REG_INSET_L3_DST_IP4_SHIFT 35\n+#define I40E_REG_INSET_L3_DST_IP4_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_L3_DST_IP4_SHIFT)\n+#define I40E_X722_REG_INSET_L3_SRC_IP4_SHIFT 49\n+#define I40E_X722_REG_INSET_L3_SRC_IP4_MASK I40E_MASK(0x3ULL, I40E_X722_REG_INSET_L3_SRC_IP4_SHIFT)\n+#define I40E_X722_REG_INSET_L3_DST_IP4_SHIFT 41\n+#define I40E_X722_REG_INSET_L3_DST_IP4_MASK I40E_MASK(0x3ULL, I40E_X722_REG_INSET_L3_DST_IP4_SHIFT)\n+#define I40E_X722_REG_INSET_L3_IP4_PROTO_SHIFT 52\n+#define I40E_X722_REG_INSET_L3_IP4_PROTO_MASK I40E_MASK(0x1ULL, I40E_X722_REG_INSET_L3_IP4_PROTO_SHIFT)\n+#define I40E_X722_REG_INSET_L3_IP4_TTL_SHIFT 52\n+#define I40E_X722_REG_INSET_L3_IP4_TTL_MASK I40E_MASK(0x1ULL, I40E_X722_REG_INSET_L3_IP4_TTL_SHIFT)\n+#define I40E_REG_INSET_L3_IP4_TOS_SHIFT 54\n+#define I40E_REG_INSET_L3_IP4_TOS_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP4_TOS_SHIFT)\n+#define I40E_REG_INSET_L3_IP4_PROTO_SHIFT 50\n+#define I40E_REG_INSET_L3_IP4_PROTO_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP4_PROTO_SHIFT)\n+#define I40E_REG_INSET_L3_IP4_TTL_SHIFT 50\n+#define I40E_REG_INSET_L3_IP4_TTL_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP4_TTL_SHIFT)\n+#define I40E_REG_INSET_L3_SRC_IP6_SHIFT 43\n+#define I40E_REG_INSET_L3_SRC_IP6_MASK I40E_MASK(0xFFULL, I40E_REG_INSET_L3_SRC_IP6_SHIFT)\n+#define I40E_REG_INSET_L3_DST_IP6_SHIFT 35\n+#define I40E_REG_INSET_L3_DST_IP6_MASK I40E_MASK(0xFFULL, I40E_REG_INSET_L3_DST_IP6_SHIFT)\n+#define I40E_REG_INSET_L3_IP6_TC_SHIFT 54\n+#define I40E_REG_INSET_L3_IP6_TC_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP6_TC_SHIFT)\n+#define I40E_REG_INSET_L3_IP6_NEXT_HDR_SHIFT 51\n+#define I40E_REG_INSET_L3_IP6_NEXT_HDR_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP6_NEXT_HDR_SHIFT)\n+#define I40E_REG_INSET_L3_IP6_HOP_LIMIT_SHIFT 51\n+#define I40E_REG_INSET_L3_IP6_HOP_LIMIT_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP6_HOP_LIMIT_SHIFT)\n+#define I40E_REG_INSET_L4_SRC_PORT_SHIFT 34\n+#define I40E_REG_INSET_L4_SRC_PORT_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L4_SRC_PORT_SHIFT)\n+#define I40E_REG_INSET_L4_DST_PORT_SHIFT 33\n+#define I40E_REG_INSET_L4_DST_PORT_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L4_DST_PORT_SHIFT)\n+#define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG_SHIFT 31\n+#define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG_SHIFT)\n+#define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC_SHIFT 22\n+#define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC_MASK I40E_MASK(0x7ULL, I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC_SHIFT)\n+#define I40E_REG_INSET_TUNNEL_L2_INNER_SRC_MAC_SHIFT 11\n+#define I40E_REG_INSET_TUNNEL_L2_INNER_SRC_MAC_MASK I40E_MASK(0x7ULL, I40E_REG_INSET_TUNNEL_L2_INNER_SRC_MAC_SHIFT)\n+#define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT_SHIFT 21\n+#define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT_SHIFT)\n+#define I40E_REG_INSET_TUNNEL_ID_SHIFT 18\n+#define I40E_REG_INSET_TUNNEL_ID_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_TUNNEL_ID_SHIFT)\n+#define I40E_REG_INSET_LAST_ETHER_TYPE_SHIFT 14\n+#define I40E_REG_INSET_LAST_ETHER_TYPE_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_LAST_ETHER_TYPE_SHIFT)\n+#define I40E_REG_INSET_TUNNEL_L3_SRC_IP4_SHIFT 8\n+#define I40E_REG_INSET_TUNNEL_L3_SRC_IP4_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_TUNNEL_L3_SRC_IP4_SHIFT)\n+#define I40E_REG_INSET_TUNNEL_L3_DST_IP4_SHIFT 6\n+#define I40E_REG_INSET_TUNNEL_L3_DST_IP4_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_TUNNEL_L3_DST_IP4_SHIFT)\n+#define I40E_REG_INSET_TUNNEL_L3_DST_IP6_SHIFT 6\n+#define I40E_REG_INSET_TUNNEL_L3_DST_IP6_MASK I40E_MASK(0xFFULL, I40E_REG_INSET_TUNNEL_L3_DST_IP6_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD1_SHIFT 13\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD1_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD1_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD2_SHIFT 12\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD2_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD2_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD3_SHIFT 11\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD3_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD3_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD4_SHIFT 10\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD4_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD4_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD5_SHIFT 9\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD5_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD5_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD6_SHIFT 8\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD6_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD6_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD7_SHIFT 7\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD7_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD7_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD8_SHIFT 6\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORD8_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD8_SHIFT)\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORDS_SHIFT 6\n+#define I40E_REG_INSET_FLEX_PAYLOAD_WORDS_MASK I40E_MASK(0xFFULL, I40E_REG_INSET_FLEX_PAYLOAD_WORDS_SHIFT)\n+#define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL\n+\n #define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30\n #define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)\n #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30\n", "prefixes": [ "v4", "28/36" ] }