Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/64407/?format=api
http://patches.dpdk.org/api/patches/64407/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200110130011.6244-1-gnandiba@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200110130011.6244-1-gnandiba@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200110130011.6244-1-gnandiba@amd.com", "date": "2020-01-10T13:00:11", "name": "[v2,2/2] net/axgbe: auto-negotiation support enabled for 1Gbps", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f558e65fca49792fcaaa4cf5e725f6b4609d7e08", "submitter": { "id": 1566, "url": "http://patches.dpdk.org/api/people/1566/?format=api", "name": null, "email": "gnandiba@amd.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200110130011.6244-1-gnandiba@amd.com/mbox/", "series": [ { "id": 8051, "url": "http://patches.dpdk.org/api/series/8051/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8051", "date": "2020-01-10T12:59:37", "name": "[v2,1/2] net/axgbe: 1/2.5Gbps support enabled for axgbe", "version": 2, "mbox": "http://patches.dpdk.org/series/8051/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64407/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/64407/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6BBBDA04F9;\n\tFri, 10 Jan 2020 14:00:36 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 443B61EA21;\n\tFri, 10 Jan 2020 14:00:36 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2061.outbound.protection.outlook.com [40.107.220.61])\n by dpdk.org (Postfix) with ESMTP id ED5211EA12\n for <dev@dpdk.org>; Fri, 10 Jan 2020 14:00:33 +0100 (CET)", "from DM6PR12MB3948.namprd12.prod.outlook.com (10.255.172.208) by\n DM6PR12MB3835.namprd12.prod.outlook.com (10.255.173.140) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.2623.9; Fri, 10 Jan 2020 13:00:31 +0000", "from DM6PR12MB3948.namprd12.prod.outlook.com\n ([fe80::b84f:565d:8588:aade]) by DM6PR12MB3948.namprd12.prod.outlook.com\n ([fe80::b84f:565d:8588:aade%3]) with mapi id 15.20.2623.013; Fri, 10 Jan 2020\n 13:00:31 +0000", "from amar-Wallaby.amd.com (165.204.156.251) by\n MA1PR0101CA0068.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::30) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2623.9 via Frontend\n Transport; Fri, 10 Jan 2020 13:00:30 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=OeShHzqo10jZK0DoVtRpeP19NLSTXKRBgwi7/OdF3AId65jKFN3IiPR5JWzJVwSmBayxQsHjDZihEQzAd64DHGAp/x+QUhhNMltgW39UasGi3BYB45zG1riH+wynkumRkk/dhUPjkExH8+kDwi5RI9S7JZATdoJ6jTsZqGV61wt3jG1B2FQZpcNHHzSww3OZw4ClaRp9i3fTIc4VuvUqNr3XWCKtFmQxoASYtQPZ34IjHBXu8Ck31xEgQfr2MX/kkig/FlMzc2bHGPCBB6qbdOGeCw6STBcBIBLmqt9scauBmn8Sg9CGVjKGmbc876/ewD1dOJ/JF2T3gsIqONHYbg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=CtXjM5QIWOW8lUv71kZAy2oGJCQer88SnHg+ROt2gys=;\n b=DGVQ33DoR5ZSN5kSddgMFZpPdUVB7CYWDJe+ZoiQ2hZjViYSEBPM7v/CdpQ4sM8PYazccbjq4U6CqhN8InJpQ6UDjsrvIrKH/XcFD6CoXuYePTXBOooOLFpf4Mj5KfWv2OM8bsI8/oj92UHTPUi34wGEBFmzNXeRscKT4DKA8ADjq4OmYuDyHd6flNrXRoI0TCb0+5EkbZzuTSyqXkc9Kv5fpoIKJhTUCULT9dSQlxxu+ocHAwH03FEtaiZ2LG6YDTGdeS7CjqT+BzZ9ACUPdSOJXiJq90PQxNEFHip9d5rnl0GRT87oLBdbA92F0C/F67vPxn66hTKUp9URb6h7Qw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass\n header.d=amd.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=CtXjM5QIWOW8lUv71kZAy2oGJCQer88SnHg+ROt2gys=;\n b=n0F4FIzfLD1Elbo4dveCPHumIQf7Xs6HsqqkLVFDnq3ajjeF7Rk5wqehFtAG3gmazIUkYGiTRxf6VbcP6nmvND6Q5CgoJ9tYXD4PDYCN0j9wwXwQqAf2I4YhsjNYAIYtX6kLy0RI0ff39HQsyTOT1Rvm/9cmVQHPJoSU+26k5Lo=", "Authentication-Results": "spf=none (sender IP is )\n smtp.mailfrom=Girish.Nandibasappa@amd.com;", "From": "gnandiba@amd.com", "To": "dev@dpdk.org", "Date": "Fri, 10 Jan 2020 18:30:11 +0530", "Message-Id": "<20200110130011.6244-1-gnandiba@amd.com>", "X-Mailer": [ "git-send-email 2.17.1", "git-send-email 2.17.1" ], "Content-Type": "text/plain", "X-ClientProxiedBy": "MA1PR0101CA0068.INDPRD01.PROD.OUTLOOK.COM\n (2603:1096:a00:20::30) To DM6PR12MB3948.namprd12.prod.outlook.com\n (2603:10b6:5:1c4::16)", "MIME-Version": "1.0", "X-Originating-IP": "[165.204.156.251]", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-HT": "Tenant", "X-MS-Office365-Filtering-Correlation-Id": "31427ef2-977e-4d1e-ee63-08d795cd12e2", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3835:", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB38353612D186F531A27AD926E1380@DM6PR12MB3835.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:186;", "X-Forefront-PRVS": "02788FF38E", "X-Forefront-Antispam-Report": "SFV:NSPM;\n SFS:(10009020)(4636009)(376002)(39860400002)(346002)(136003)(396003)(366004)(189003)(199004)(2906002)(52116002)(7696005)(478600001)(66476007)(66556008)(30864003)(66946007)(1076003)(186003)(36756003)(9686003)(16526019)(316002)(26005)(6486002)(6666004)(2616005)(8676002)(81156014)(956004)(5660300002)(6916009)(81166006)(8936002);\n DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR12MB3835;\n H:DM6PR12MB3948.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en;\n PTR:InfoNoRecords; MX:1; A:1;", "Received-SPF": "None (protection.outlook.com: amd.com does not designate\n permitted sender hosts)", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n yp9oytIcuDVkW5755dWYw0Rtjl6sZ3xTC+dONBL35WxVqzEjhqHaRL1Pvf2cqa3V7814YE8op5RdDLcCK6lpq1lWSM6ZzbYicZdWpkIauE988s4vGdBJsQz+XyrrcCcXqjr1j4Oohexr0g6s5uM4e+ep5UUgZ532vgWGencrQhre23T5XCpPjBUjEf+Dw3i/WIEtpT4bR/YKrr2euf8oTMYJBmtNS8IxoO4n5NwpA6/BcnKqxWq64aFQNWMh2beT6fyfXnMCTDUmhM6zLCHE44dDhQXlwS9DD6hqy6jfmJmuhTvIKCDNMVlmT7n4HEdQwLJTHTt+XjIP+DAHyZJg819JVx0YfiE0s8/AtfUzdSTteDEfqqlJm+oR7HoAdQGA1s4pfcxiatAA7fzXn8YVfDNKD3BrVTgcUqDFACmUg5LamBA+wfpkT2Bv7OIeHxcL", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 31427ef2-977e-4d1e-ee63-08d795cd12e2", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Jan 2020 13:00:31.5649 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n VJIHBbR7Q1FkfYNfsga8vMv+ONc9QzXdiwCPE2GQBPrqovwKrfVM//mJJTHUso1IGSdqieFp58gJGS2DUBQdzg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3835", "Subject": "[dpdk-dev] [PATCH v2 2/2] net/axgbe: auto-negotiation support\n\tenabled for 1Gbps", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Girish Nandibasappa <girish.nandibasappa@amd.com>\n\nAdded CL37 Auto-neg support for 1Gbps interface in\naxgbe DPDK driver\n\nSigned-off-by: Girish Nandibasappa <girish.nandibasappa@amd.com>\n---\n drivers/net/axgbe/axgbe_common.h | 1 +\n drivers/net/axgbe/axgbe_mdio.c | 192 +++++++++++++++++++++++++++--\n drivers/net/axgbe/axgbe_phy_impl.c | 37 ++++++\n 3 files changed, 219 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h\nindex 34f60f156..99fa92d5c 100644\n--- a/drivers/net/axgbe/axgbe_common.h\n+++ b/drivers/net/axgbe/axgbe_common.h\n@@ -1296,6 +1296,7 @@\n #define AXGBE_AN_CL37_PCS_MODE_BASEX\t0x00\n #define AXGBE_AN_CL37_PCS_MODE_SGMII\t0x04\n #define AXGBE_AN_CL37_TX_CONFIG_MASK\t0x08\n+#define AXGBE_AN_CL37_MII_CTRL_8BIT 0x0100\n \n #define AXGBE_PMA_CDR_TRACK_EN_MASK\t0x01\n #define AXGBE_PMA_CDR_TRACK_EN_OFF\t0x00\ndiff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c\nindex 2721e5cc9..3902b1ec3 100644\n--- a/drivers/net/axgbe/axgbe_mdio.c\n+++ b/drivers/net/axgbe/axgbe_mdio.c\n@@ -29,6 +29,19 @@ static void axgbe_an37_disable_interrupts(struct axgbe_port *pdata)\n \tXMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);\n }\n \n+static void axgbe_an37_enable_interrupts(struct axgbe_port *pdata)\n+{\n+\tunsigned int reg;\n+\n+\treg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);\n+\treg |= AXGBE_PCS_CL37_BP;\n+\tXMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);\n+\n+\treg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);\n+\treg |= AXGBE_AN_CL37_INT_MASK;\n+\tXMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);\n+}\n+\n static void axgbe_an73_clear_interrupts(struct axgbe_port *pdata)\n {\n \tXMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);\n@@ -54,7 +67,7 @@ static void axgbe_an_enable_interrupts(struct axgbe_port *pdata)\n \t\tbreak;\n \tcase AXGBE_AN_MODE_CL37:\n \tcase AXGBE_AN_MODE_CL37_SGMII:\n-\t\tPMD_DRV_LOG(ERR, \"Unsupported AN_MOD_37\\n\");\n+\t\taxgbe_an37_enable_interrupts(pdata);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -254,6 +267,12 @@ static void axgbe_an37_set(struct axgbe_port *pdata, bool enable,\n \tXMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);\n }\n \n+static void axgbe_an37_restart(struct axgbe_port *pdata)\n+{\n+\taxgbe_an37_enable_interrupts(pdata);\n+\taxgbe_an37_set(pdata, true, true);\n+}\n+\n static void axgbe_an37_disable(struct axgbe_port *pdata)\n {\n \taxgbe_an37_set(pdata, false, false);\n@@ -302,7 +321,7 @@ static void axgbe_an_restart(struct axgbe_port *pdata)\n \t\tbreak;\n \tcase AXGBE_AN_MODE_CL37:\n \tcase AXGBE_AN_MODE_CL37_SGMII:\n-\t\tPMD_DRV_LOG(ERR, \"Unsupported AN_MODE_CL37\\n\");\n+\t\taxgbe_an37_restart(pdata);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -321,7 +340,7 @@ static void axgbe_an_disable(struct axgbe_port *pdata)\n \t\tbreak;\n \tcase AXGBE_AN_MODE_CL37:\n \tcase AXGBE_AN_MODE_CL37_SGMII:\n-\t\tPMD_DRV_LOG(ERR, \"Unsupported AN_MODE_CL37\\n\");\n+\t\taxgbe_an37_disable(pdata);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -573,6 +592,53 @@ static void axgbe_an73_state_machine(struct axgbe_port *pdata)\n \taxgbe_an73_enable_interrupts(pdata);\n }\n \n+static void axgbe_an37_state_machine(struct axgbe_port *pdata)\n+{\n+\tenum axgbe_an cur_state = pdata->an_state;\n+\n+\tif (!pdata->an_int)\n+\t\treturn;\n+\tif (pdata->an_int & AXGBE_AN_CL37_INT_CMPLT) {\n+\t\tpdata->an_state = AXGBE_AN_COMPLETE;\n+\t\tpdata->an_int &= ~AXGBE_AN_CL37_INT_CMPLT;\n+\n+\t/* If SGMII is enabled, check the link status */\n+\t\tif (pdata->an_mode == AXGBE_AN_MODE_CL37_SGMII &&\n+\t\t !(pdata->an_status & AXGBE_SGMII_AN_LINK_STATUS))\n+\t\t\tpdata->an_state = AXGBE_AN_NO_LINK;\n+\t}\n+\n+\tcur_state = pdata->an_state;\n+\n+\tswitch (pdata->an_state) {\n+\tcase AXGBE_AN_READY:\n+\t\tbreak;\n+\tcase AXGBE_AN_COMPLETE:\n+\t\tbreak;\n+\tcase AXGBE_AN_NO_LINK:\n+\t\tbreak;\n+\tdefault:\n+\t\tpdata->an_state = AXGBE_AN_ERROR;\n+\t\tbreak;\n+\t}\n+\n+\tif (pdata->an_state == AXGBE_AN_ERROR) {\n+\t\tPMD_DRV_LOG(ERR, \"error during auto-negotiation, state=%u\\n\",\n+\t\t\t cur_state);\n+\t\tpdata->an_int = 0;\n+\t\taxgbe_an37_clear_interrupts(pdata);\n+\t}\n+\n+\tif (pdata->an_state >= AXGBE_AN_COMPLETE) {\n+\t\tpdata->an_result = pdata->an_state;\n+\t\tpdata->an_state = AXGBE_AN_READY;\n+\t\tif (pdata->phy_if.phy_impl.an_post)\n+\t\t\tpdata->phy_if.phy_impl.an_post(pdata);\n+\t}\n+\n+\taxgbe_an37_enable_interrupts(pdata);\n+}\n+\n static void axgbe_an73_isr(struct axgbe_port *pdata)\n {\n \t/* Disable AN interrupts */\n@@ -580,6 +646,7 @@ static void axgbe_an73_isr(struct axgbe_port *pdata)\n \n \t/* Save the interrupt(s) that fired */\n \tpdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);\n+\taxgbe_an73_clear_interrupts(pdata);\n \n \tif (pdata->an_int) {\n \t\t/* Clear the interrupt(s) that fired and process them */\n@@ -593,6 +660,29 @@ static void axgbe_an73_isr(struct axgbe_port *pdata)\n \t}\n }\n \n+static void axgbe_an37_isr(struct axgbe_port *pdata)\n+{\n+\tunsigned int reg = 0;\n+\t/* Disable AN interrupts */\n+\taxgbe_an37_disable_interrupts(pdata);\n+\n+\t/* Save the interrupt(s) that fired */\n+\treg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);\n+\tpdata->an_int = reg & AXGBE_AN_CL37_INT_MASK;\n+\tpdata->an_status = reg & ~AXGBE_AN_CL37_INT_MASK;\n+\taxgbe_an37_clear_interrupts(pdata);\n+\n+\tif (pdata->an_int & 0x01) {\n+\t\t/* Clear the interrupt(s) that fired and process them */\n+\t\treg &= ~AXGBE_AN_CL37_INT_MASK;\n+\t\tXMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);\n+\t\taxgbe_an37_state_machine(pdata);\n+\t} else {\n+\t\t/* Enable AN interrupts */\n+\t\taxgbe_an37_enable_interrupts(pdata);\n+\t}\n+}\n+\n static void axgbe_an_isr(struct axgbe_port *pdata)\n {\n \tswitch (pdata->an_mode) {\n@@ -602,7 +692,7 @@ static void axgbe_an_isr(struct axgbe_port *pdata)\n \t\tbreak;\n \tcase AXGBE_AN_MODE_CL37:\n \tcase AXGBE_AN_MODE_CL37_SGMII:\n-\t\tPMD_DRV_LOG(ERR, \"AN_MODE_37 not supported\\n\");\n+\t\taxgbe_an37_isr(pdata);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -614,6 +704,48 @@ static void axgbe_an_combined_isr(struct axgbe_port *pdata)\n \taxgbe_an_isr(pdata);\n }\n \n+static void axgbe_an37_init(struct axgbe_port *pdata)\n+{\n+\tunsigned int advertising;\n+\tunsigned int reg = 0;\n+\n+\tadvertising = pdata->phy_if.phy_impl.an_advertising(pdata);\n+\n+\treg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);\n+\tif (advertising & ADVERTISED_Pause)\n+\t\treg |= 0x100;\n+\telse\n+\t\treg &= ~0x100;\n+\tif (advertising & ADVERTISED_Asym_Pause)\n+\t\treg |= 0x80;\n+\telse\n+\t\treg &= ~0x80;\n+\n+\t/* Full duplex, but not half */\n+\treg |= AXGBE_AN_CL37_FD_MASK;\n+\treg &= ~AXGBE_AN_CL37_HD_MASK;\n+\n+\tXMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);\n+\n+\t/* Set up the Control register */\n+\treg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);\n+\treg &= ~AXGBE_AN_CL37_TX_CONFIG_MASK;\n+\treg &= ~AXGBE_AN_CL37_PCS_MODE_MASK;\n+\n+\tswitch (pdata->an_mode) {\n+\tcase AXGBE_AN_MODE_CL37:\n+\t\treg |= AXGBE_AN_CL37_PCS_MODE_BASEX;\n+\t\tbreak;\n+\tcase AXGBE_AN_MODE_CL37_SGMII:\n+\t\treg |= AXGBE_AN_CL37_PCS_MODE_SGMII;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treg |= AXGBE_AN_CL37_MII_CTRL_8BIT;\n+\tXMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);\n+}\n+\n static void axgbe_an73_init(struct axgbe_port *pdata)\n {\n \tunsigned int advertising, reg;\n@@ -673,7 +805,7 @@ static void axgbe_an_init(struct axgbe_port *pdata)\n \t\tbreak;\n \tcase AXGBE_AN_MODE_CL37:\n \tcase AXGBE_AN_MODE_CL37_SGMII:\n-\t\tPMD_DRV_LOG(ERR, \"Unsupported AN_CL37\\n\");\n+\t\taxgbe_an37_init(pdata);\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -782,9 +914,6 @@ static int __axgbe_phy_config_aneg(struct axgbe_port *pdata)\n \t/* Disable and stop any in progress auto-negotiation */\n \taxgbe_an_disable_all(pdata);\n \n-\t/* Clear any auto-negotitation interrupts */\n-\taxgbe_an_clear_interrupts_all(pdata);\n-\n \tpdata->an_result = AXGBE_AN_READY;\n \tpdata->an_state = AXGBE_AN_READY;\n \tpdata->kr_state = AXGBE_RX_BPA;\n@@ -792,6 +921,7 @@ static int __axgbe_phy_config_aneg(struct axgbe_port *pdata)\n \n \t/* Re-enable auto-negotiation interrupt */\n \trte_intr_enable(&pdata->pci_dev->intr_handle);\n+\taxgbe_an37_enable_interrupts(pdata);\n \n \taxgbe_an_init(pdata);\n \taxgbe_an_restart(pdata);\n@@ -875,10 +1005,26 @@ static void axgbe_phy_status_result(struct axgbe_port *pdata)\n \taxgbe_set_mode(pdata, mode);\n }\n \n+static int autoneg_time_out(unsigned long autoneg_start_time)\n+{\n+\tunsigned long autoneg_timeout;\n+\tunsigned long ticks;\n+\n+\tautoneg_timeout = autoneg_start_time + (AXGBE_LINK_TIMEOUT *\n+\t\t\t\t\t\t2 * rte_get_timer_hz());\n+\tticks = rte_get_timer_cycles();\n+\tif (time_after(ticks, autoneg_timeout))\n+\t\treturn 1;\n+\telse\n+\t\treturn 0;\n+}\n+\n static void axgbe_phy_status(struct axgbe_port *pdata)\n {\n \tunsigned int link_aneg;\n-\tint an_restart;\n+\tint an_restart, ret;\n+\tunsigned int reg = 0;\n+\tunsigned long autoneg_start_time;\n \n \tif (axgbe_test_bit(AXGBE_LINK_ERR, &pdata->dev_state)) {\n \t\tpdata->phy.link = 0;\n@@ -896,8 +1042,32 @@ static void axgbe_phy_status(struct axgbe_port *pdata)\n \n \tif (pdata->phy.link) {\n \t\tif (link_aneg && !axgbe_phy_aneg_done(pdata)) {\n-\t\t\taxgbe_check_link_timeout(pdata);\n-\t\t\treturn;\n+\t\t\tif (axgbe_cur_mode(pdata) == AXGBE_MODE_SGMII_1000) {\n+\t\t\t\t/*autoneg not complete, so re-intializing*/\n+\t\t\t\t/* and restarting it*/\n+\t\t\t\taxgbe_an_init(pdata);\n+\t\t\t\taxgbe_an_restart(pdata);\n+\t\t\t\treg = XMDIO_READ(pdata, MDIO_MMD_VEND2,\n+\t\t\t\t\t\t MDIO_VEND2_AN_STAT);\n+\t\t\t\tautoneg_start_time = rte_get_timer_cycles();\n+\t\t\t\t/*poll for autoneg to complete*/\n+\t\t\t\twhile (!(reg & AXGBE_AN_CL37_INT_CMPLT)) {\n+\t\t\t\t\tret =\n+\t\t\t\t\tautoneg_time_out(autoneg_start_time);\n+\t\t\t\t\tif (ret)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\treg = XMDIO_READ(pdata,\n+\t\t\t\t\t\t\t MDIO_MMD_VEND2,\n+\t\t\t\t\t\t\t MDIO_VEND2_AN_STAT);\n+\t\t\t\t\tif (reg & AXGBE_AN_CL37_INT_CMPLT) {\n+\t\t\t\t\t\taxgbe_an37_isr(pdata);\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\taxgbe_check_link_timeout(pdata);\n+\t\t\t\treturn;\n+\t\t\t}\n \t\t}\n \t\taxgbe_phy_status_result(pdata);\n \t\tif (axgbe_test_bit(AXGBE_LINK_INIT, &pdata->dev_state))\ndiff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c\nindex f0dc11695..a324a2bc9 100644\n--- a/drivers/net/axgbe/axgbe_phy_impl.c\n+++ b/drivers/net/axgbe/axgbe_phy_impl.c\n@@ -957,6 +957,41 @@ static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata)\n \treturn mode;\n }\n \n+static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata)\n+{\n+\tenum axgbe_mode mode;\n+\n+\tpdata->phy.lp_advertising |= ADVERTISED_Autoneg;\n+\tpdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;\n+\n+\tif (pdata->phy.pause_autoneg)\n+\t\taxgbe_phy_phydev_flowctrl(pdata);\n+\n+\tswitch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) {\n+\tcase AXGBE_SGMII_AN_LINK_SPEED_100:\n+\t\tif (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {\n+\t\t\tpdata->phy.lp_advertising |= ADVERTISED_100baseT_Full;\n+\t\t\tmode = AXGBE_MODE_SGMII_100;\n+\t\t} else {\n+\t\t\tmode = AXGBE_MODE_UNKNOWN;\n+\t\t}\n+\t\tbreak;\n+\tcase AXGBE_SGMII_AN_LINK_SPEED_1000:\n+\t\tif (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) {\n+\t\t\tpdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full;\n+\t\t\tmode = AXGBE_MODE_SGMII_1000;\n+\t\t} else {\n+\t\t\t/* Half-duplex not supported */\n+\t\t\tmode = AXGBE_MODE_UNKNOWN;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tmode = AXGBE_MODE_UNKNOWN;\n+\t\tbreak;\n+\t}\n+\treturn mode;\n+}\n+\n static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata)\n {\n \tswitch (pdata->an_mode) {\n@@ -966,6 +1001,7 @@ static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata)\n \t\treturn axgbe_phy_an73_redrv_outcome(pdata);\n \tcase AXGBE_AN_MODE_CL37:\n \tcase AXGBE_AN_MODE_CL37_SGMII:\n+\t\treturn axgbe_phy_an37_sgmii_outcome(pdata);\n \tdefault:\n \t\treturn AXGBE_MODE_UNKNOWN;\n \t}\n@@ -1957,6 +1993,7 @@ static int axgbe_phy_start(struct axgbe_port *pdata)\n \tdefault:\n \t\tbreak;\n \t}\n+\tpdata->phy.advertising &= axgbe_phy_an_advertising(pdata);\n \n \treturn ret;\n }\n", "prefixes": [ "v2", "2/2" ] }{ "id": 64407, "url": "