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GET /api/patches/64297/?format=api
{ "id": 64297, "url": "http://patches.dpdk.org/api/patches/64297/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1578500161-20156-5-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1578500161-20156-5-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1578500161-20156-5-git-send-email-viacheslavo@mellanox.com", "date": "2020-01-08T16:16:01", "name": "[4/4] net/mlx5: engage free on completion queue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d4eb3174161882ef600128d4b1feadab2ea8065b", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1578500161-20156-5-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 8020, "url": "http://patches.dpdk.org/api/series/8020/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=8020", "date": "2020-01-08T16:15:57", "name": "net/mlx5: remove Tx descriptor reserved field usage", "version": 1, "mbox": "http://patches.dpdk.org/series/8020/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64297/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/64297/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C8F82A04F3;\n\tWed, 8 Jan 2020 17:16:52 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4B6E31DACF;\n\tWed, 8 Jan 2020 17:16:35 +0100 (CET)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id A78DD1DAC7\n for <dev@dpdk.org>; Wed, 8 Jan 2020 17:16:33 +0100 (CET)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n viacheslavo@mellanox.com)\n with ESMTPS (AES256-SHA encrypted); 8 Jan 2020 18:16:32 +0200", "from pegasus11.mtr.labs.mlnx (pegasus11.mtr.labs.mlnx\n [10.210.16.104])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 008GGWtV000915;\n Wed, 8 Jan 2020 18:16:32 +0200", "from pegasus11.mtr.labs.mlnx (localhost [127.0.0.1])\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 008GGWWV020241;\n Wed, 8 Jan 2020 16:16:32 GMT", "(from viacheslavo@localhost)\n by pegasus11.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 008GGWI2020240;\n Wed, 8 Jan 2020 16:16:32 GMT" ], "X-Authentication-Warning": "pegasus11.mtr.labs.mlnx: viacheslavo set sender to\n viacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "matan@mellanox.com, rasland@mellanox.com, orika@mellanox.com", "Date": "Wed, 8 Jan 2020 16:16:01 +0000", "Message-Id": "<1578500161-20156-5-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1578500161-20156-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1578500161-20156-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 4/4] net/mlx5: engage free on completion queue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The free on completion queue keeps the indices of elts array,\nall mbuf stored below this index should be freed on arrival\nof normal send completion. In debug version it also contains\nan index of completed transmitting descriptor (WQE) to check\nqueues synchronization.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5_rxtx.c | 33 +++++++++++++++++----------------\n drivers/net/mlx5/mlx5_rxtx.h | 6 ++----\n drivers/net/mlx5/mlx5_txq.c | 4 ----\n 3 files changed, 19 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex b7b40ac..b11c5eb 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -2043,8 +2043,7 @@ enum mlx5_txcmp_code {\n \t\tuint16_t tail;\n \n \t\ttxq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);\n-\t\ttail = ((volatile struct mlx5_wqe_cseg *)\n-\t\t\t(txq->wqes + (txq->wqe_pi & txq->wqe_m)))->misc;\n+\t\ttail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];\n \t\tif (likely(tail != txq->elts_tail)) {\n \t\t\tmlx5_tx_free_elts(txq, tail, olx);\n \t\t\tassert(tail == txq->elts_tail);\n@@ -2095,6 +2094,7 @@ enum mlx5_txcmp_code {\n \t\t\t * here, before we might perform SQ reset.\n \t\t\t */\n \t\t\trte_wmb();\n+\t\t\ttxq->cq_ci = ci;\n \t\t\tret = mlx5_tx_error_cqe_handle\n \t\t\t\t(txq, (volatile struct mlx5_err_cqe *)cqe);\n \t\t\tif (unlikely(ret < 0)) {\n@@ -2108,17 +2108,18 @@ enum mlx5_txcmp_code {\n \t\t\t/*\n \t\t\t * We are going to fetch all entries with\n \t\t\t * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.\n+\t\t\t * The send queue is supposed to be empty.\n \t\t\t */\n \t\t\t++ci;\n+\t\t\ttxq->cq_pi = ci;\n+\t\t\tlast_cqe = NULL;\n \t\t\tcontinue;\n \t\t}\n \t\t/* Normal transmit completion. */\n+\t\tassert(ci != txq->cq_pi);\n+\t\tassert((txq->fcqs[ci & txq->cqe_m] >> 16) == cqe->wqe_counter);\n \t\t++ci;\n \t\tlast_cqe = cqe;\n-#ifndef NDEBUG\n-\t\tif (txq->cq_pi)\n-\t\t\t--txq->cq_pi;\n-#endif\n \t\t/*\n \t\t * We have to restrict the amount of processed CQEs\n \t\t * in one tx_burst routine call. The CQ may be large\n@@ -2127,7 +2128,7 @@ enum mlx5_txcmp_code {\n \t\t * multiple iterations may introduce significant\n \t\t * latency.\n \t\t */\n-\t\tif (--count == 0)\n+\t\tif (likely(--count == 0))\n \t\t\tbreak;\n \t} while (true);\n \tif (likely(ci != txq->cq_ci)) {\n@@ -2177,15 +2178,15 @@ enum mlx5_txcmp_code {\n \t\t/* Request unconditional completion on last WQE. */\n \t\tlast->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n \t\t\t\t\t MLX5_COMP_MODE_OFFSET);\n-\t\t/* Save elts_head in unused \"immediate\" field of WQE. */\n-\t\tlast->cseg.misc = head;\n-\t\t/*\n-\t\t * A CQE slot must always be available. Count the\n-\t\t * issued CEQ \"always\" request instead of production\n-\t\t * index due to here can be CQE with errors and\n-\t\t * difference with ci may become inconsistent.\n-\t\t */\n-\t\tassert(txq->cqe_s > ++txq->cq_pi);\n+\t\t/* Save elts_head in dedicated free on completion queue. */\n+#ifdef NDEBUG\n+\t\ttxq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;\n+#else\n+\t\ttxq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |\n+\t\t\t\t\t(last->cseg.opcode >> 8) << 16;\n+#endif\n+\t\t/* A CQE slot must always be available. */\n+\t\tassert((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);\n \t}\n }\n \ndiff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h\nindex ee1895b..e362b4a 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.h\n+++ b/drivers/net/mlx5/mlx5_rxtx.h\n@@ -273,9 +273,7 @@ struct mlx5_txq_data {\n \tuint16_t wqe_thres; /* WQE threshold to request completion in CQ. */\n \t/* WQ related fields. */\n \tuint16_t cq_ci; /* Consumer index for completion queue. */\n-#ifndef NDEBUG\n-\tuint16_t cq_pi; /* Counter of issued CQE \"always\" requests. */\n-#endif\n+\tuint16_t cq_pi; /* Production index for completion queue. */\n \tuint16_t cqe_s; /* Number of CQ elements. */\n \tuint16_t cqe_m; /* Mask for CQ indices. */\n \t/* CQ related fields. */\n@@ -298,7 +296,7 @@ struct mlx5_txq_data {\n \tstruct mlx5_wqe *wqes; /* Work queue. */\n \tstruct mlx5_wqe *wqes_end; /* Work queue array limit. */\n #ifdef NDEBUG\n-\tuint32_t *fcqs; /* Free completion queue. */\n+\tuint16_t *fcqs; /* Free completion queue. */\n #else\n \tuint32_t *fcqs; /* Free completion queue (debug extended). */\n #endif\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 5e6a605..c750082 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -717,9 +717,7 @@ struct mlx5_txq_obj *\n \ttxq_data->cq_db = cq_info.dbrec;\n \ttxq_data->cqes = (volatile struct mlx5_cqe *)cq_info.buf;\n \ttxq_data->cq_ci = 0;\n-#ifndef NDEBUG\n \ttxq_data->cq_pi = 0;\n-#endif\n \ttxq_data->wqe_ci = 0;\n \ttxq_data->wqe_pi = 0;\n \ttxq_data->wqe_comp = 0;\n@@ -735,8 +733,6 @@ struct mlx5_txq_obj *\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\ttxq_data->fcq_head = 0;\n-\ttxq_data->fcq_tail = 0;\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t/*\n \t * If using DevX need to query and store TIS transport domain value.\n", "prefixes": [ "4/4" ] }