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GET /api/patches/64218/?format=api
{ "id": 64218, "url": "http://patches.dpdk.org/api/patches/64218/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20200106033851.43978-4-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200106033851.43978-4-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200106033851.43978-4-qi.z.zhang@intel.com", "date": "2020-01-06T03:38:42", "name": "[v2,03/12] net/ice/base: do not wait for PE unit to load", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "49b969fb5664920d5b1ced555d381a85a9e22b80", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20200106033851.43978-4-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 7984, "url": "http://patches.dpdk.org/api/series/7984/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7984", "date": "2020-01-06T03:38:39", "name": "base code update", "version": 2, "mbox": "http://patches.dpdk.org/series/7984/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/64218/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/64218/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C612A04F1;\n\tMon, 6 Jan 2020 04:36:15 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 956461D539;\n\tMon, 6 Jan 2020 04:35:53 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by dpdk.org (Postfix) with ESMTP id 2CC821D517\n for <dev@dpdk.org>; Mon, 6 Jan 2020 04:35:50 +0100 (CET)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 05 Jan 2020 19:35:49 -0800", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga007.fm.intel.com with ESMTP; 05 Jan 2020 19:35:48 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.69,401,1571727600\"; d=\"scan'208\";a=\"216726336\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n Bruce Allan <bruce.w.allan@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 6 Jan 2020 11:38:42 +0800", "Message-Id": "<20200106033851.43978-4-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20200106033851.43978-1-qi.z.zhang@intel.com>", "References": "<20191205123847.39579-1-qi.z.zhang@intel.com>\n <20200106033851.43978-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 03/12] net/ice/base: do not wait for PE unit\n\tto load", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "When RDMA is not enabled, when checking for completion of a CORER or GLOBR\ndo not wait for the PE unit to be loaded (indicated by GLNVM_ULD register's\nPE_DONE bit being set) since that does not happen and will cause issues\nsuch as failing to initialize the device.\n\nSigned-off-by: Bruce Allan <bruce.w.allan@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 19 ++++++++++++-------\n 1 file changed, 12 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 4ba3ab202..319b00f75 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -645,7 +645,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \n \tice_clear_pxe_mode(hw);\n \n-\n \tstatus = ice_get_caps(hw);\n \tif (status)\n \t\tgoto err_unroll_cqinit;\n@@ -666,7 +665,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)\n \t\tgoto err_unroll_alloc;\n \n \thw->evb_veb = true;\n-\n \t/* Query the allocated resources for Tx scheduler */\n \tstatus = ice_sched_query_res_alloc(hw);\n \tif (status) {\n@@ -785,7 +783,7 @@ void ice_deinit_hw(struct ice_hw *hw)\n */\n enum ice_status ice_check_reset(struct ice_hw *hw)\n {\n-\tu32 cnt, reg = 0, grst_delay;\n+\tu32 cnt, reg = 0, grst_delay, uld_mask;\n \n \t/* Poll for Device Active state in case a recent CORER, GLOBR,\n \t * or EMPR has occurred. The grst delay value is in 100ms units.\n@@ -807,13 +805,20 @@ enum ice_status ice_check_reset(struct ice_hw *hw)\n \t\treturn ICE_ERR_RESET_FAILED;\n \t}\n \n-#define ICE_RESET_DONE_MASK\t(GLNVM_ULD_CORER_DONE_M | \\\n-\t\t\t\t GLNVM_ULD_GLOBR_DONE_M)\n+#define ICE_RESET_DONE_MASK\t(GLNVM_ULD_PCIER_DONE_M |\\\n+\t\t\t\t GLNVM_ULD_PCIER_DONE_1_M |\\\n+\t\t\t\t GLNVM_ULD_CORER_DONE_M |\\\n+\t\t\t\t GLNVM_ULD_GLOBR_DONE_M |\\\n+\t\t\t\t GLNVM_ULD_POR_DONE_M |\\\n+\t\t\t\t GLNVM_ULD_POR_DONE_1_M |\\\n+\t\t\t\t GLNVM_ULD_PCIER_DONE_2_M)\n+\n+\tuld_mask = ICE_RESET_DONE_MASK;\n \n \t/* Device is Active; check Global Reset processes are done */\n \tfor (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {\n-\t\treg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;\n-\t\tif (reg == ICE_RESET_DONE_MASK) {\n+\t\treg = rd32(hw, GLNVM_ULD) & uld_mask;\n+\t\tif (reg == uld_mask) {\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n \t\t\t\t \"Global reset processes done. %d\\n\", cnt);\n \t\t\tbreak;\n", "prefixes": [ "v2", "03/12" ] }