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GET /api/patches/63591/?format=api
{ "id": 63591, "url": "http://patches.dpdk.org/api/patches/63591/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191205123847.39579-10-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191205123847.39579-10-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191205123847.39579-10-qi.z.zhang@intel.com", "date": "2019-12-05T12:38:44", "name": "[09/12] net/ice/base: change fdir desc preparation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fa141a453b77baf4c6c163a2d954b6275c135533", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "http://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191205123847.39579-10-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 7737, "url": "http://patches.dpdk.org/api/series/7737/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7737", "date": "2019-12-05T12:38:35", "name": "base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/7737/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63591/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/63591/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5616DA04F2;\n\tThu, 5 Dec 2019 13:37:12 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 483721BFBF;\n\tThu, 5 Dec 2019 13:36:08 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by dpdk.org (Postfix) with ESMTP id 1C6FD1BF9B\n for <dev@dpdk.org>; Thu, 5 Dec 2019 13:35:54 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n 05 Dec 2019 04:35:54 -0800", "from dpdk51.sh.intel.com ([10.67.110.245])\n by fmsmga008.fm.intel.com with ESMTP; 05 Dec 2019 04:35:53 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.69,281,1571727600\"; d=\"scan'208\";a=\"209122760\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "xiaolong.ye@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Kiran Patil <kiran.patil@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Thu, 5 Dec 2019 20:38:44 +0800", "Message-Id": "<20191205123847.39579-10-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20191205123847.39579-1-qi.z.zhang@intel.com>", "References": "<20191205123847.39579-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 09/12] net/ice/base: change fdir desc preparation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Change internal implemenatation of how FD filter programming desc\nis prepared. This is to minimize the amount of code needed to prep\nthe FD filter programming desc (avoid memcpy, etc...) and just use\npredefined shifts and mask. This type of change are needed to expedite\nFD setup during data path (ADQ uses this codepath during initial\nflow setup) and it will also be useful when adding side-band\nflow-director filter.\n\nSigned-off-by: Kiran Patil <kiran.patil@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_fdir.c | 92 ++++++++++++++++++++++++-----------------\n 1 file changed, 55 insertions(+), 37 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c\nindex 37b388169..87fa0afba 100644\n--- a/drivers/net/ice/base/ice_fdir.c\n+++ b/drivers/net/ice/base/ice_fdir.c\n@@ -352,35 +352,6 @@ static const struct ice_fdir_base_pkt ice_fdir_pkt[] = {\n \n #define ICE_FDIR_NUM_PKT ARRAY_SIZE(ice_fdir_pkt)\n \n-/* Flow Direcotr (FD) filter program descriptor Context */\n-static const struct ice_ctx_ele ice_fd_fltr_desc_ctx_info[] = {\n-\t\t\t\t\t /* Field\t\tWidth\tLSB */\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, qindex,\t\t11,\t0),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, comp_q,\t\t1,\t11),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, comp_report,\t2,\t12),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, fd_space,\t\t2,\t14),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, cnt_index,\t\t13,\t16),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, cnt_ena,\t\t2,\t29),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, evict_ena,\t\t1,\t31),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, toq,\t\t3,\t32),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, toq_prio,\t\t3,\t35),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, dpu_recipe,\t\t2,\t38),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, drop,\t\t1,\t40),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_prio,\t\t3,\t41),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_mdid,\t\t4,\t44),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, flex_val,\t\t16,\t48),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, dtype,\t\t4,\t64),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, pcmd,\t\t1,\t68),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, desc_prof_prio,\t3,\t69),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, desc_prof,\t\t6,\t72),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, fd_vsi,\t\t10,\t78),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, swap,\t\t1,\t88),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid_prio,\t\t3,\t89),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid_mdid,\t\t4,\t92),\n-\tICE_CTX_STORE(ice_fd_fltr_desc_ctx, fdid,\t\t32,\t96),\n-\t{ 0 }\n-};\n-\n /**\n * ice_set_dflt_val_fd_desc\n * @fd_fltr_ctx: pointer to fd filter descriptor\n@@ -455,19 +426,66 @@ ice_fdir_get_prgm_desc(struct ice_hw *hw, struct ice_fdir_fltr *input,\n \n /**\n * ice_set_fd_desc_val\n- * @fd_fltr_ctx: pointer to fd filter descriptor context\n+ * @ctx: pointer to fd filter descriptor context\n * @fdir_desc: populated with fd filter descriptor values\n */\n void\n-ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *fd_fltr_ctx,\n+ice_set_fd_desc_val(struct ice_fd_fltr_desc_ctx *ctx,\n \t\t struct ice_fltr_desc *fdir_desc)\n {\n-\tu64 ctx_buf[2] = { 0 };\n-\n-\tice_set_ctx((u8 *)fd_fltr_ctx, (u8 *)ctx_buf,\n-\t\t ice_fd_fltr_desc_ctx_info);\n-\tfdir_desc->qidx_compq_space_stat = CPU_TO_LE64(ctx_buf[0]);\n-\tfdir_desc->dtype_cmd_vsi_fdid = CPU_TO_LE64(ctx_buf[1]);\n+\tu64 qword;\n+\n+\t/* prep QW0 of FD filter programming desc */\n+\tqword = ((u64)ctx->qindex << ICE_FXD_FLTR_QW0_QINDEX_S) &\n+\t\tICE_FXD_FLTR_QW0_QINDEX_M;\n+\tqword |= ((u64)ctx->comp_q << ICE_FXD_FLTR_QW0_COMP_Q_S) &\n+\t\t ICE_FXD_FLTR_QW0_COMP_Q_M;\n+\tqword |= ((u64)ctx->comp_report << ICE_FXD_FLTR_QW0_COMP_REPORT_S) &\n+\t\t ICE_FXD_FLTR_QW0_COMP_REPORT_M;\n+\tqword |= ((u64)ctx->fd_space << ICE_FXD_FLTR_QW0_FD_SPACE_S) &\n+\t\t ICE_FXD_FLTR_QW0_FD_SPACE_M;\n+\tqword |= ((u64)ctx->cnt_index << ICE_FXD_FLTR_QW0_STAT_CNT_S) &\n+\t\t ICE_FXD_FLTR_QW0_STAT_CNT_M;\n+\tqword |= ((u64)ctx->cnt_ena << ICE_FXD_FLTR_QW0_STAT_ENA_S) &\n+\t\t ICE_FXD_FLTR_QW0_STAT_ENA_M;\n+\tqword |= ((u64)ctx->evict_ena << ICE_FXD_FLTR_QW0_EVICT_ENA_S) &\n+\t\t ICE_FXD_FLTR_QW0_EVICT_ENA_M;\n+\tqword |= ((u64)ctx->toq << ICE_FXD_FLTR_QW0_TO_Q_S) &\n+\t\t ICE_FXD_FLTR_QW0_TO_Q_M;\n+\tqword |= ((u64)ctx->toq_prio << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) &\n+\t\t ICE_FXD_FLTR_QW0_TO_Q_PRI_M;\n+\tqword |= ((u64)ctx->dpu_recipe << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) &\n+\t\t ICE_FXD_FLTR_QW0_DPU_RECIPE_M;\n+\tqword |= ((u64)ctx->drop << ICE_FXD_FLTR_QW0_DROP_S) &\n+\t\t ICE_FXD_FLTR_QW0_DROP_M;\n+\tqword |= ((u64)ctx->flex_prio << ICE_FXD_FLTR_QW0_FLEX_PRI_S) &\n+\t\t ICE_FXD_FLTR_QW0_FLEX_PRI_M;\n+\tqword |= ((u64)ctx->flex_mdid << ICE_FXD_FLTR_QW0_FLEX_MDID_S) &\n+\t\t ICE_FXD_FLTR_QW0_FLEX_MDID_M;\n+\tqword |= ((u64)ctx->flex_val << ICE_FXD_FLTR_QW0_FLEX_VAL_S) &\n+\t\t ICE_FXD_FLTR_QW0_FLEX_VAL_M;\n+\tfdir_desc->qidx_compq_space_stat = CPU_TO_LE64(qword);\n+\n+\t/* prep QW1 of FD filter programming desc */\n+\tqword = ((u64)ctx->dtype << ICE_FXD_FLTR_QW1_DTYPE_S) &\n+\t\tICE_FXD_FLTR_QW1_DTYPE_M;\n+\tqword |= ((u64)ctx->pcmd << ICE_FXD_FLTR_QW1_PCMD_S) &\n+\t\t ICE_FXD_FLTR_QW1_PCMD_M;\n+\tqword |= ((u64)ctx->desc_prof_prio << ICE_FXD_FLTR_QW1_PROF_PRI_S) &\n+\t\t ICE_FXD_FLTR_QW1_PROF_PRI_M;\n+\tqword |= ((u64)ctx->desc_prof << ICE_FXD_FLTR_QW1_PROF_S) &\n+\t\t ICE_FXD_FLTR_QW1_PROF_M;\n+\tqword |= ((u64)ctx->fd_vsi << ICE_FXD_FLTR_QW1_FD_VSI_S) &\n+\t\t ICE_FXD_FLTR_QW1_FD_VSI_M;\n+\tqword |= ((u64)ctx->swap << ICE_FXD_FLTR_QW1_SWAP_S) &\n+\t\t ICE_FXD_FLTR_QW1_SWAP_M;\n+\tqword |= ((u64)ctx->fdid_prio << ICE_FXD_FLTR_QW1_FDID_PRI_S) &\n+\t\t ICE_FXD_FLTR_QW1_FDID_PRI_M;\n+\tqword |= ((u64)ctx->fdid_mdid << ICE_FXD_FLTR_QW1_FDID_MDID_S) &\n+\t\t ICE_FXD_FLTR_QW1_FDID_MDID_M;\n+\tqword |= ((u64)ctx->fdid << ICE_FXD_FLTR_QW1_FDID_S) &\n+\t\t ICE_FXD_FLTR_QW1_FDID_M;\n+\tfdir_desc->dtype_cmd_vsi_fdid = CPU_TO_LE64(qword);\n }\n \n /**\n", "prefixes": [ "09/12" ] }