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GET /api/patches/63155/?format=api
{ "id": 63155, "url": "http://patches.dpdk.org/api/patches/63155/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1574244727-6003-2-git-send-email-joyce.kong@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1574244727-6003-2-git-send-email-joyce.kong@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1574244727-6003-2-git-send-email-joyce.kong@arm.com", "date": "2019-11-20T10:12:02", "name": "[v4,1/6] lib/eal: implement the family of rte bit operation APIs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "edba9c20ae377b627fbbde58de539a60387ec290", "submitter": { "id": 970, "url": "http://patches.dpdk.org/api/people/970/?format=api", "name": "Joyce Kong", "email": "joyce.kong@arm.com" }, "delegate": { "id": 24651, "url": "http://patches.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1574244727-6003-2-git-send-email-joyce.kong@arm.com/mbox/", "series": [ { "id": 7544, "url": "http://patches.dpdk.org/api/series/7544/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=7544", "date": "2019-11-20T10:12:01", "name": "implement common rte bit operation APIs in PMDs", "version": 4, "mbox": "http://patches.dpdk.org/series/7544/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/63155/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/63155/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 014E0A04C1;\n\tWed, 20 Nov 2019 11:12:33 +0100 (CET)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5F9A67CBC;\n\tWed, 20 Nov 2019 11:12:30 +0100 (CET)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id EFB9E5F13\n for <dev@dpdk.org>; Wed, 20 Nov 2019 11:12:28 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5825C31B;\n Wed, 20 Nov 2019 02:12:28 -0800 (PST)", "from net-arm-thunderx2-01.test.ast.arm.com\n (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A79FC3F52E;\n Wed, 20 Nov 2019 02:12:24 -0800 (PST)" ], "From": "Joyce Kong <joyce.kong@arm.com>", "To": "dev@dpdk.org", "Cc": "nd@arm.com, thomas@monjalon.net, jerinj@marvell.com,\n stephen@networkplumber.org, mb@smartsharesystems.com,\n david.marchand@redhat.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com,\n ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com,\n xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com,\n zhouguoyang@huawei.com", "Date": "Wed, 20 Nov 2019 18:12:02 +0800", "Message-Id": "<1574244727-6003-2-git-send-email-joyce.kong@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": [ "<1574244727-6003-1-git-send-email-joyce.kong@arm.com>", "<1571125801-45773-1-git-send-email-joyce.kong@arm.com>" ], "References": [ "<1574244727-6003-1-git-send-email-joyce.kong@arm.com>", "<1571125801-45773-1-git-send-email-joyce.kong@arm.com>" ], "Subject": "[dpdk-dev] [PATCH v4 1/6] lib/eal: implement the family of rte bit\n\toperation APIs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "There are a lot functions of bit operations scattered and\nduplicated in PMDs, consolidating them into a common API\nfamily is necessary. Furthermore, when the bit operation\nis applied to the IO devices, use __ATOMIC_ACQ_REL to\nensure the ordering for io bit operation.\n\nSigned-off-by: Joyce Kong <joyce.kong@arm.com>\nReviewed-by: Gavin Hu <gavin.hu@arm.com>\nReviewed-by: Phil Yang <phil.yang@arm.com>\n---\n MAINTAINERS | 5 +\n doc/api/doxy-api-index.md | 5 +-\n lib/librte_eal/common/Makefile | 1 +\n lib/librte_eal/common/include/rte_bitops.h | 474 +++++++++++++++++++++++++++++\n lib/librte_eal/common/meson.build | 3 +-\n 5 files changed, 485 insertions(+), 3 deletions(-)\n create mode 100644 lib/librte_eal/common/include/rte_bitops.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex f2fdb93..4ee2712 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -233,6 +233,11 @@ M: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\n F: lib/librte_eal/common/include/rte_bitmap.h\n F: app/test/test_bitmap.c\n \n+Bitops\n+M: Joyce Kong <joyce.kong@arm.com>\n+F: lib/librte_eal/common/include/rte_bitops.h\n+F: app/test/test_bitops.c\n+\n MCSlock - EXPERIMENTAL\n M: Phil Yang <phil.yang@arm.com>\n F: lib/librte_eal/common/include/generic/rte_mcslock.h\ndiff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md\nindex dff496b..ade7c01 100644\n--- a/doc/api/doxy-api-index.md\n+++ b/doc/api/doxy-api-index.md\n@@ -133,12 +133,13 @@ The public API headers are grouped by topics:\n [BPF] (@ref rte_bpf.h)\n \n - **containers**:\n+ [bitmap] (@ref rte_bitmap.h),\n+ [bitops] (@ref rte_bitops.h),\n [mbuf] (@ref rte_mbuf.h),\n [mbuf pool ops] (@ref rte_mbuf_pool_ops.h),\n [ring] (@ref rte_ring.h),\n [stack] (@ref rte_stack.h),\n- [tailq] (@ref rte_tailq.h),\n- [bitmap] (@ref rte_bitmap.h)\n+ [tailq] (@ref rte_tailq.h)\n \n - **packet framework**:\n * [port] (@ref rte_port.h):\ndiff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex c2c6d92..dd025c1 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -19,6 +19,7 @@ INC += rte_malloc.h rte_keepalive.h rte_time.h\n INC += rte_service.h rte_service_component.h\n INC += rte_bitmap.h rte_vfio.h rte_hypervisor.h rte_test.h\n INC += rte_reciprocal.h rte_fbarray.h rte_uuid.h\n+INC += rte_bitops.h\n \n GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h\n GENERIC_INC += rte_memcpy.h rte_cpuflags.h\ndiff --git a/lib/librte_eal/common/include/rte_bitops.h b/lib/librte_eal/common/include/rte_bitops.h\nnew file mode 100644\nindex 0000000..34158d1\n--- /dev/null\n+++ b/lib/librte_eal/common/include/rte_bitops.h\n@@ -0,0 +1,474 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Arm Limited\n+ */\n+\n+#ifndef _RTE_BITOPS_H_\n+#define _RTE_BITOPS_H_\n+\n+/**\n+ * @file\n+ * Bit Operations\n+ *\n+ * This file defines a API for bit operations without/with memory ordering.\n+ */\n+\n+#include <stdint.h>\n+#include <rte_debug.h>\n+#include <rte_compat.h>\n+\n+/*---------------------------- 32 bit operations ----------------------------*/\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Get the target bit from a 32-bit value without memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The target bit.\n+ */\n+__rte_experimental\n+static inline uint32_t\n+rte_get_bit32_relaxed(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\treturn __atomic_load_n(addr, __ATOMIC_RELAXED) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Set the target bit in a 32-bit value to 1 without memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to set.\n+ * @param addr\n+ * The address holding the bit.\n+ */\n+__rte_experimental\n+static inline void\n+rte_set_bit32_relaxed(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\t__atomic_fetch_or(addr, mask, __ATOMIC_RELAXED);\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Clear the target bit in a 32-bit value to 0 without memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to clear.\n+ * @param addr\n+ * The address holding the bit.\n+ */\n+__rte_experimental\n+static inline void\n+rte_clear_bit32_relaxed(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\t__atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED);\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 32-bit value, then set it to 1 without\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and set.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint32_t\n+rte_test_and_set_bit32_relaxed(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\treturn __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 32-bit value, then clear it to 0 without\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and clear.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint32_t\n+rte_test_and_clear_bit32_relaxed(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\treturn __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Get the target bit from a 32-bit value with memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The target bit.\n+ */\n+__rte_experimental\n+static inline uint32_t\n+rte_get_bit32(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\treturn __atomic_load_n(addr, __ATOMIC_ACQUIRE) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Set the target bit in a 32-bit value to 1 with memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to set.\n+ * @param addr\n+ * The address holding the bit.\n+ */\n+__rte_experimental\n+static inline void\n+rte_set_bit32(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\t__atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL);\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Clear the target bit in a 32-bit value to 0 with memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to clear.\n+ * @param addr\n+ * The address holding the bit.\n+ */\n+__rte_experimental\n+static inline void\n+rte_clear_bit32(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\t__atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL);\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 32-bit value, then set it to 1 with\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and set.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint32_t\n+rte_test_and_set_bit32(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\treturn __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 32-bit value, then clear it to 0 with\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and clear.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint32_t\n+rte_test_and_clear_bit32(unsigned int nr, uint32_t *addr)\n+{\n+\tRTE_ASSERT(nr < 32);\n+\n+\tuint32_t mask = UINT32_C(1) << nr;\n+\treturn __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL) & mask;\n+}\n+\n+/*---------------------------- 64 bit operations ----------------------------*/\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Get the target bit from a 64-bit value without memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The target bit.\n+ */\n+__rte_experimental\n+static inline uint64_t\n+rte_get_bit64_relaxed(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\treturn __atomic_load_n(addr, __ATOMIC_RELAXED) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Set the target bit in a 64-bit value to 1 without memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to set.\n+ * @param addr\n+ * The address holding the bit.\n+ */\n+__rte_experimental\n+static inline void\n+rte_set_bit64_relaxed(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\t__atomic_fetch_or(addr, mask, __ATOMIC_RELAXED);\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Clear the target bit in a 64-bit value to 0 without memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to clear.\n+ * @param addr\n+ * The address holding the bit.\n+ */\n+__rte_experimental\n+static inline void\n+rte_clear_bit64_relaxed(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\t__atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED);\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 64-bit value, then set it to 1 without\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and set.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint64_t\n+rte_test_and_set_bit64_relaxed(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\treturn __atomic_fetch_or(addr, mask, __ATOMIC_RELAXED) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 64-bit value, then clear it to 0 without\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and clear.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint64_t\n+rte_test_and_clear_bit64_relaxed(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\treturn __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Get the target bit from a 64-bit value with memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The target bit.\n+ */\n+__rte_experimental\n+static inline uint64_t\n+rte_get_bit64(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\treturn __atomic_load_n(addr, __ATOMIC_ACQUIRE) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Set the target bit in a 64-bit value to 1 with memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to set.\n+ * @param addr\n+ * The address holding the bit.\n+ */\n+__rte_experimental\n+static inline void\n+rte_set_bit64(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\t__atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL);\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Clear the target bit in a 64-bit value to 0 with memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to clear.\n+ * @param addr\n+ * The address holding the bit.\n+ */\n+__rte_experimental\n+static inline void\n+rte_clear_bit64(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\t__atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL);\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 64-bit value, then set it to 1 with\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and set.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint64_t\n+rte_test_and_set_bit64(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\treturn __atomic_fetch_or(addr, mask, __ATOMIC_ACQ_REL) & mask;\n+}\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Return the original bit from a 64-bit value, then clear it to 0 with\n+ * memory ordering.\n+ *\n+ * @param nr\n+ * The target bit to get and clear.\n+ * @param addr\n+ * The address holding the bit.\n+ * @return\n+ * The original bit.\n+ */\n+__rte_experimental\n+static inline uint64_t\n+rte_test_and_clear_bit64(unsigned int nr, uint64_t *addr)\n+{\n+\tRTE_ASSERT(nr < 64);\n+\n+\tuint64_t mask = UINT64_C(1) << nr;\n+\treturn __atomic_fetch_and(addr, ~mask, __ATOMIC_ACQ_REL) & mask;\n+}\n+#endif /* _RTE_BITOPS_H_ */\ndiff --git a/lib/librte_eal/common/meson.build b/lib/librte_eal/common/meson.build\nindex d6a149b..8a5197b 100644\n--- a/lib/librte_eal/common/meson.build\n+++ b/lib/librte_eal/common/meson.build\n@@ -50,9 +50,10 @@ common_objs += eal_common_arch_objs\n \n common_headers = files(\n \t'include/rte_alarm.h',\n+\t'include/rte_bitmap.h',\n+\t'include/rte_bitops.h',\n \t'include/rte_branch_prediction.h',\n \t'include/rte_bus.h',\n-\t'include/rte_bitmap.h',\n \t'include/rte_class.h',\n \t'include/rte_common.h',\n \t'include/rte_compat.h',\n", "prefixes": [ "v4", "1/6" ] }