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GET /api/patches/61315/?format=api
{ "id": 61315, "url": "http://patches.dpdk.org/api/patches/61315/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1571239544-13387-2-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1571239544-13387-2-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1571239544-13387-2-git-send-email-anoobj@marvell.com", "date": "2019-10-16T15:25:34", "name": "[v3,01/11] crypto/octeontx2: add PMD skeleton", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2e51f1f9c0f0883ab532f14941b4f93923188b97", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1571239544-13387-2-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 6887, "url": "http://patches.dpdk.org/api/series/6887/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6887", "date": "2019-10-16T15:25:33", "name": "add OCTEON TX2 crypto PMD", "version": 3, "mbox": "http://patches.dpdk.org/series/6887/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/61315/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/61315/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D57DA1E985;\n\tWed, 16 Oct 2019 17:27:36 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 52DCD1E982\n\tfor <dev@dpdk.org>; Wed, 16 Oct 2019 17:27:35 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx9GFP9Y1020088; Wed, 16 Oct 2019 08:27:34 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2vnpmbkg88-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tWed, 16 Oct 2019 08:27:34 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tWed, 16 Oct 2019 08:27:33 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Wed, 16 Oct 2019 08:27:33 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.60])\n\tby maili.marvell.com (Postfix) with ESMTP id 16C563F7040;\n\tWed, 16 Oct 2019 08:27:28 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-type : content-transfer-encoding; s=pfpt0818;\n\tbh=xlleqo1Gf91Rl9yzOThBhxBoAkyypEqidwzT0YPIxLI=;\n\tb=TZHt8zzymgtE6zl11Cx+JlPmKpPN16rsTBWhyYXthaPvzKBOLrdM8Bi6tMK+h9MjQThg\n\tQ+HIlS5C+4/aRyVFLlUohwtAuwMoT/RpVzfiWkBzj1eGPYO/3GLx2uIbs2C2fxHCKFl+\n\ttquAQwBiC7W4MVdr1VHNpITTSZclfgu/arV/6evM4+8Lo7AJZvbpfLOcA6iEbv0F++X/\n\twvoAYmx5u71DmH0tE2AcEx9zoq2i3DmFk9k71VWHkLQyCRKbwA09ZhQlj+oXJoHxecX2\n\teCyChnQSh1IcxAqVbtFzofndhDphomDyvzsmTke4f3kCEWwSz48dDNz2l7pdlHAOsmz+\n\taA== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Fiona Trahe <fiona.trahe@intel.com>, \n\tJerin Jacob <jerinj@marvell.com>, Narayana Prasad <pathreya@marvell.com>,\n\tShally Verma <shallyv@marvell.com>,\n\tAnkur Dwivedi <adwivedi@marvell.com>, \n\tKanaka Durga Kotamarthy <kkotamarthy@marvell.com>, Sunila Sahu\n\t<ssahu@marvell.com>,\n\tTejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Wed, 16 Oct 2019 20:55:34 +0530", "Message-ID": "<1571239544-13387-2-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1571239544-13387-1-git-send-email-anoobj@marvell.com>", "References": "<1570970402-20278-1-git-send-email-anoobj@marvell.com>\n\t<1571239544-13387-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-10-16_06:2019-10-16,2019-10-16 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 01/11] crypto/octeontx2: add PMD skeleton", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Adding OCTEON TX2 crypto PMD skeleton. Enabling the driver by default\nin common_base.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n MAINTAINERS | 7 ++\n config/common_base | 5 +\n doc/guides/cryptodevs/features/octeontx2.ini | 8 ++\n doc/guides/cryptodevs/index.rst | 1 +\n doc/guides/cryptodevs/octeontx2.rst | 93 +++++++++++++++++\n doc/guides/platform/octeontx2.rst | 3 +\n doc/guides/rel_notes/release_19_11.rst | 6 ++\n drivers/common/Makefile | 5 +-\n drivers/crypto/Makefile | 1 +\n drivers/crypto/meson.build | 21 +++-\n drivers/crypto/octeontx2/Makefile | 37 +++++++\n drivers/crypto/octeontx2/meson.build | 29 ++++++\n drivers/crypto/octeontx2/otx2_cryptodev.c | 111 +++++++++++++++++++++\n drivers/crypto/octeontx2/otx2_cryptodev.h | 29 ++++++\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 27 +++++\n drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 12 +++\n .../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 +\n mk/rte.app.mk | 6 +-\n 18 files changed, 400 insertions(+), 5 deletions(-)\n create mode 100644 doc/guides/cryptodevs/features/octeontx2.ini\n create mode 100644 doc/guides/cryptodevs/octeontx2.rst\n create mode 100644 drivers/crypto/octeontx2/Makefile\n create mode 100644 drivers/crypto/octeontx2/meson.build\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n create mode 100644 drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex f8a56e2..b064e48 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -980,6 +980,13 @@ F: drivers/crypto/nitrox/\n F: doc/guides/cryptodevs/nitrox.rst\n F: doc/guides/cryptodevs/features/nitrox.ini\n \n+Marvell OCTEON TX2 crypto\n+M: Ankur Dwivedi <adwivedi@marvell.com>\n+M: Anoob Joseph <anoobj@marvell.com>\n+F: drivers/crypto/octeontx2/\n+F: doc/guides/cryptodevs/octeontx2.rst\n+F: doc/guides/cryptodevs/features/octeontx2.ini\n+\n Null Crypto\n M: Declan Doherty <declan.doherty@intel.com>\n F: drivers/crypto/null/\ndiff --git a/config/common_base b/config/common_base\nindex e843a21..895db64 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -592,6 +592,11 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4\n CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y\n \n #\n+# Compile PMD for Marvell OCTEON TX2 crypto device\n+#\n+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y\n+\n+#\n # Compile PMD for QuickAssist based devices - see docs for details\n #\n CONFIG_RTE_LIBRTE_PMD_QAT=y\ndiff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini\nnew file mode 100644\nindex 0000000..35c9bee\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/octeontx2.ini\n@@ -0,0 +1,8 @@\n+;\n+; Supported features of the 'octeontx2' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Symmetric crypto = Y\n+HW Accelerated = Y\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex d1e0d32..a67ed5a 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -19,6 +19,7 @@ Crypto Device Drivers\n dpaa_sec\n kasumi\n octeontx\n+ octeontx2\n openssl\n mvsam\n nitrox\ndiff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst\nnew file mode 100644\nindex 0000000..10f578a\n--- /dev/null\n+++ b/doc/guides/cryptodevs/octeontx2.rst\n@@ -0,0 +1,93 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2019 Marvell International Ltd.\n+\n+\n+Marvell OCTEON TX2 Crypto Poll Mode Driver\n+==========================================\n+\n+The OCTEON TX2 crypto poll mode driver provides support for offloading\n+cryptographic operations to cryptographic accelerator units on the\n+**OCTEON TX2** :sup:`®` family of processors (CN9XXX).\n+\n+More information about OCTEON TX2 SoCs may be obtained from `<https://www.marvell.com>`_\n+\n+Features\n+--------\n+\n+The OCTEON TX2 crypto PMD has support for:\n+\n+Installation\n+------------\n+\n+The OCTEON TX2 crypto PMD may be compiled natively on an OCTEON TX2 platform or\n+cross-compiled on an x86 platform.\n+\n+Enable OCTEON TX2 crypto PMD in your config file:\n+\n+* ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y``\n+\n+Refer to :doc:`../platform/octeontx2` for instructions to build your DPDK\n+application.\n+\n+.. note::\n+\n+ The OCTEON TX2 crypto PMD uses services from the kernel mode OCTEON TX2\n+ crypto PF driver in linux. This driver is included in the OCTEON TX SDK.\n+\n+Initialization\n+--------------\n+\n+List the CPT PF devices available on your OCTEON TX2 platform:\n+\n+.. code-block:: console\n+\n+ lspci -d:a0fd\n+\n+``a0fd`` is the CPT PF device id. You should see output similar to:\n+\n+.. code-block:: console\n+\n+ 0002:10:00.0 Class 1080: Device 177d:a0fd\n+\n+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:\n+\n+.. code-block:: console\n+\n+ echo 1 > /sys/bus/pci/drivers/octeontx2-cpt/0002:10:00.0/sriov_numvfs\n+\n+Bind the CPT VF device to the vfio_pci driver:\n+\n+.. code-block:: console\n+\n+ echo '177d a0fe' > /sys/bus/pci/drivers/vfio-pci/new_id\n+ echo 0002:10:00.1 > /sys/bus/pci/devices/0002:10:00.1/driver/unbind\n+ echo 0002:10:00.1 > /sys/bus/pci/drivers/vfio-pci/bind\n+\n+Another way to bind the VF would be to use the ``dpdk-devbind.py`` script:\n+\n+.. code-block:: console\n+\n+ cd <dpdk directory>\n+ ./usertools/dpdk-devbind.py -u 0002:10:00.1\n+ ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1\n+\n+.. note::\n+\n+ Ensure that sufficient huge pages are available for your application::\n+\n+ echo 8 > /sys/kernel/mm/hugepages/hugepages-524288kB/nr_hugepages\n+\n+ Refer to :ref:`linux_gsg_hugepages` for more details.\n+\n+Debugging Options\n+-----------------\n+\n+.. _table_octeontx2_crypto_debug_options:\n+\n+.. table:: OCTEON TX2 crypto PMD debug options\n+\n+ +---+------------+-------------------------------------------------------+\n+ | # | Component | EAL log command |\n+ +===+============+=======================================================+\n+ | 1 | CPT | --log-level='pmd\\.crypto\\.octeontx2,8' |\n+ +---+------------+-------------------------------------------------------+\ndiff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst\nindex 1ee5eac..1c7d98f 100644\n--- a/doc/guides/platform/octeontx2.rst\n+++ b/doc/guides/platform/octeontx2.rst\n@@ -131,6 +131,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.\n #. **DMA Rawdev Driver**\n See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.\n \n+#. **Crypto Device Driver**\n+ See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.\n+\n Procedure to Setup Platform\n ---------------------------\n \ndiff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst\nindex f1673e1..94c5a97 100644\n--- a/doc/guides/rel_notes/release_19_11.rst\n+++ b/doc/guides/rel_notes/release_19_11.rst\n@@ -131,6 +131,12 @@ New Features\n Added eBPF JIT support for arm64 architecture to improve the eBPF program\n performance.\n \n+* **Added Marvell OCTEON TX2 crypto PMD**\n+\n+ Added a new PMD driver for h/w crypto offload block on ``OCTEON TX2`` SoC.\n+\n+ See :doc:`../cryptodevs/octeontx2` for more details\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/common/Makefile b/drivers/common/Makefile\nindex bc6f972..1ff033b 100644\n--- a/drivers/common/Makefile\n+++ b/drivers/common/Makefile\n@@ -4,7 +4,9 @@\n \n include $(RTE_SDK)/mk/rte.vars.mk\n \n-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)\n+CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)\n+CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n+ifneq (,$(findstring y,$(CPT-y)))\n DIRS-y += cpt\n endif\n \n@@ -12,6 +14,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO\n DIRS-y += octeontx\n endif\n OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)\n+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n ifeq ($(findstring y,$(OCTEONTX2-y)),y)\n DIRS-y += octeontx2\n endif\ndiff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile\nindex 7129bcf..8b00857 100644\n--- a/drivers/crypto/Makefile\n+++ b/drivers/crypto/Makefile\n@@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += octeontx2\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g\ndiff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build\nindex 1a358ff..229debd 100644\n--- a/drivers/crypto/meson.build\n+++ b/drivers/crypto/meson.build\n@@ -1,9 +1,24 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n-drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec',\n-\t'kasumi', 'mvsam', 'nitrox', 'null', 'octeontx', 'openssl', 'qat',\n-\t'scheduler', 'snow3g', 'virtio', 'zuc']\n+drivers = ['aesni_gcm',\n+\t 'aesni_mb',\n+\t 'caam_jr',\n+\t 'ccp',\n+\t 'dpaa_sec',\n+\t 'dpaa2_sec',\n+\t 'kasumi',\n+\t 'mvsam',\n+\t 'nitrox',\n+\t 'null',\n+\t 'octeontx',\n+\t 'octeontx2',\n+\t 'openssl',\n+\t 'qat',\n+\t 'scheduler',\n+\t 'snow3g',\n+\t 'virtio',\n+\t 'zuc']\n \n std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps\n config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'\ndiff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile\nnew file mode 100644\nindex 0000000..3273178\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/Makefile\n@@ -0,0 +1,37 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright (C) 2019 Marvell International Ltd.\n+#\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# library name\n+LIB = librte_pmd_octeontx2_crypto.a\n+\n+# library version\n+LIBABIVER := 1\n+\n+# build flags\n+CFLAGS += $(WERROR_FLAGS)\n+\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_cryptodev\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+LDLIBS += -lrte_common_cpt -lrte_common_octeontx2\n+\n+VPATH += $(RTE_SDK)/drivers/crypto/octeontx2\n+\n+CFLAGS += -O3\n+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt\n+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n+\n+# PMD code\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c\n+\n+# export include files\n+SYMLINK-y-include +=\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_octeontx2_crypto_version.map\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build\nnew file mode 100644\nindex 0000000..2b55d2a\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/meson.build\n@@ -0,0 +1,29 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright (C) 2019 Marvell International Ltd.\n+\n+if host_machine.system() != 'linux'\n+ build = false\n+endif\n+\n+deps += ['bus_pci']\n+deps += ['common_cpt']\n+deps += ['common_octeontx2']\n+name = 'octeontx2_crypto'\n+\n+sources = files('otx2_cryptodev.c',\n+\t\t'otx2_cryptodev_ops.c')\n+\n+extra_flags = []\n+# This integrated controller runs only on a arm64 machine, remove 32bit warnings\n+if not dpdk_conf.get('RTE_ARCH_64')\n+\textra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']\n+endif\n+\n+foreach flag: extra_flags\n+\tif cc.has_argument(flag)\n+\t\tcflags += flag\n+\tendif\n+endforeach\n+\n+includes += include_directories('../../common/cpt')\n+includes += include_directories('../../common/octeontx2')\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c\nnew file mode 100644\nindex 0000000..ca9f227\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c\n@@ -0,0 +1,111 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_dev.h>\n+#include <rte_errno.h>\n+#include <rte_mempool.h>\n+#include <rte_pci.h>\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_ops.h\"\n+\n+/* CPT common headers */\n+#include \"cpt_common.h\"\n+#include \"cpt_pmd_logs.h\"\n+\n+int otx2_cpt_logtype;\n+\n+static struct rte_pci_id pci_id_cpt_table[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\t PCI_DEVID_OCTEONTX2_RVU_CPT_VF)\n+\t},\n+\t/* sentinel */\n+\t{\n+\t\t.device_id = 0\n+\t},\n+};\n+\n+static int\n+otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t\t struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_cryptodev_pmd_init_params init_params = {\n+\t\t.name = \"\",\n+\t\t.socket_id = rte_socket_id(),\n+\t\t.private_data_size = sizeof(struct otx2_cpt_vf)\n+\t};\n+\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\tstruct rte_cryptodev *dev;\n+\tint ret;\n+\n+\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n+\n+\tdev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params);\n+\tif (dev == NULL) {\n+\t\tret = -ENODEV;\n+\t\tgoto exit;\n+\t}\n+\n+\tdev->dev_ops = &otx2_cpt_ops;\n+\n+\tdev->driver_id = otx2_cryptodev_driver_id;\n+\n+\tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\t RTE_CRYPTODEV_FF_HW_ACCELERATED;\n+\n+\treturn 0;\n+\n+exit:\n+\tCPT_LOG_ERR(\"Could not create device (vendor_id: 0x%x device_id: 0x%x)\",\n+\t\t pci_dev->id.vendor_id, pci_dev->id.device_id);\n+\treturn ret;\n+}\n+\n+static int\n+otx2_cpt_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\tstruct rte_cryptodev *dev;\n+\n+\tif (pci_dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n+\n+\tdev = rte_cryptodev_pmd_get_named_dev(name);\n+\tif (dev == NULL)\n+\t\treturn -ENODEV;\n+\n+\treturn rte_cryptodev_pmd_destroy(dev);\n+}\n+\n+static struct rte_pci_driver otx2_cryptodev_pmd = {\n+\t.id_table = pci_id_cpt_table,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = otx2_cpt_pci_probe,\n+\t.remove = otx2_cpt_pci_remove,\n+};\n+\n+static struct cryptodev_driver otx2_cryptodev_drv;\n+\n+RTE_INIT(otx2_cpt_init_log);\n+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table);\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver,\n+\t\totx2_cryptodev_driver_id);\n+\n+RTE_INIT(otx2_cpt_init_log)\n+{\n+\t/* Bus level logs */\n+\totx2_cpt_logtype = rte_log_register(\"pmd.crypto.octeontx2\");\n+\tif (otx2_cpt_logtype >= 0)\n+\t\trte_log_set_level(otx2_cpt_logtype, RTE_LOG_NOTICE);\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h\nnew file mode 100644\nindex 0000000..c9fe0c8\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_CRYPTODEV_H_\n+#define _OTX2_CRYPTODEV_H_\n+\n+#include \"cpt_common.h\"\n+\n+/* Marvell OCTEON TX2 Crypto PMD device name */\n+#define CRYPTODEV_NAME_OCTEONTX2_PMD\tcrypto_octeontx2\n+\n+/**\n+ * Device private data\n+ */\n+struct otx2_cpt_vf {\n+\t/* To be populated */\n+};\n+\n+#define CPT_LOGTYPE otx2_cpt_logtype\n+\n+extern int otx2_cpt_logtype;\n+\n+/*\n+ * Crypto device driver ID\n+ */\n+uint8_t otx2_cryptodev_driver_id;\n+\n+#endif /* _OTX2_CRYPTODEV_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nnew file mode 100644\nindex 0000000..18ad470\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -0,0 +1,27 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_cryptodev_pmd.h>\n+\n+#include \"otx2_cryptodev_ops.h\"\n+\n+struct rte_cryptodev_ops otx2_cpt_ops = {\n+\t/* Device control ops */\n+\t.dev_configure = NULL,\n+\t.dev_start = NULL,\n+\t.dev_stop = NULL,\n+\t.dev_close = NULL,\n+\t.dev_infos_get = NULL,\n+\n+\t.stats_get = NULL,\n+\t.stats_reset = NULL,\n+\t.queue_pair_setup = NULL,\n+\t.queue_pair_release = NULL,\n+\t.queue_pair_count = NULL,\n+\n+\t/* Symmetric crypto ops */\n+\t.sym_session_get_size = NULL,\n+\t.sym_session_configure = NULL,\n+\t.sym_session_clear = NULL,\n+};\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\nnew file mode 100644\nindex 0000000..545614e\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n@@ -0,0 +1,12 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_CRYPTODEV_OPS_H_\n+#define _OTX2_CRYPTODEV_OPS_H_\n+\n+#include <rte_cryptodev_pmd.h>\n+\n+struct rte_cryptodev_ops otx2_cpt_ops;\n+\n+#endif /* _OTX2_CRYPTODEV_OPS_H_ */\ndiff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\nnew file mode 100644\nindex 0000000..b7b7c91\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\n@@ -0,0 +1,4 @@\n+DPDK_19.11 {\n+\n+\tlocal: *;\n+};\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex b91273f..e79f16e 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -101,7 +101,9 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUX),y)\n _LDLIBS-$(CONFIG_RTE_LIBRTE_KNI) += -lrte_kni\n endif\n \n-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)\n+OTX-CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)\n+OTX-CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n+ifeq ($(findstring y,$(OTX-CPT-y)),y)\n _LDLIBS-y += -lrte_common_cpt\n endif\n \n@@ -109,6 +111,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO\n _LDLIBS-y += -lrte_common_octeontx\n endif\n OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)\n+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD)\n@@ -270,6 +273,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -L$(ARMV8_CRYPTO_LIB_PATH) -\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += -lrte_pmd_nitrox\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += -lrte_pmd_octeontx2_crypto\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler\n ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y)\n ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)\n", "prefixes": [ "v3", "01/11" ] }