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{
    "id": 60947,
    "url": "http://patches.dpdk.org/api/patches/60947/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1570782089-182978-11-git-send-email-andy.pei@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1570782089-182978-11-git-send-email-andy.pei@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1570782089-182978-11-git-send-email-andy.pei@intel.com",
    "date": "2019-10-11T08:21:21",
    "name": "[v8,10/18] raw/ifpga: add SEU error handler",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "c05d8f81cb97d30d5d89ecef5b406e159153b7d1",
    "submitter": {
        "id": 1185,
        "url": "http://patches.dpdk.org/api/people/1185/?format=api",
        "name": "Pei, Andy",
        "email": "andy.pei@intel.com"
    },
    "delegate": {
        "id": 31221,
        "url": "http://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1570782089-182978-11-git-send-email-andy.pei@intel.com/mbox/",
    "series": [
        {
            "id": 6801,
            "url": "http://patches.dpdk.org/api/series/6801/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6801",
            "date": "2019-10-11T08:21:11",
            "name": "add PCIe AER disable and IRQ support for ipn3ke",
            "version": 8,
            "mbox": "http://patches.dpdk.org/series/6801/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/60947/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/60947/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 634E21EA5A;\n\tFri, 11 Oct 2019 10:33:44 +0200 (CEST)",
            "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n\tby dpdk.org (Postfix) with ESMTP id 908F01EA05\n\tfor <dev@dpdk.org>; Fri, 11 Oct 2019 10:33:34 +0200 (CEST)",
            "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t11 Oct 2019 01:33:34 -0700",
            "from dpdk-dipei.sh.intel.com ([10.67.110.224])\n\tby fmsmga006.fm.intel.com with ESMTP; 11 Oct 2019 01:33:32 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.67,283,1566889200\"; d=\"scan'208\";a=\"395681886\"",
        "From": "Andy Pei <andy.pei@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "rosen.xu@intel.com, tianfei.zhang@intel.com, andy.pei@intel.com,\n\txiaolong.ye@intel.com, qi.z.zhang@intel.com",
        "Date": "Fri, 11 Oct 2019 16:21:21 +0800",
        "Message-Id": "<1570782089-182978-11-git-send-email-andy.pei@intel.com>",
        "X-Mailer": "git-send-email 1.8.3.1",
        "In-Reply-To": "<1570782089-182978-1-git-send-email-andy.pei@intel.com>",
        "References": "<1569485262-457887-2-git-send-email-andy.pei@intel.com>\n\t<1570782089-182978-1-git-send-email-andy.pei@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v8 10/18] raw/ifpga: add SEU error handler",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Rosen Xu <rosen.xu@intel.com>\n\nAdd SEU interrupt support for FPGA.\n\nSigned-off-by: Tianfei zhang <tianfei.zhang@intel.com>\nSigned-off-by: Rosen Xu <rosen.xu@intel.com>\nSigned-off-by: Andy Pei <andy.pei@intel.com>\n---\n drivers/raw/ifpga/ifpga_rawdev.c | 245 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 245 insertions(+)",
    "diff": "diff --git a/drivers/raw/ifpga/ifpga_rawdev.c b/drivers/raw/ifpga/ifpga_rawdev.c\nindex 1825143..f5e6119 100644\n--- a/drivers/raw/ifpga/ifpga_rawdev.c\n+++ b/drivers/raw/ifpga/ifpga_rawdev.c\n@@ -27,6 +27,8 @@\n #include <rte_bus_vdev.h>\n \n #include \"base/opae_hw_api.h\"\n+#include \"base/opae_ifpga_hw_api.h\"\n+#include \"base/ifpga_api.h\"\n #include \"rte_rawdev.h\"\n #include \"rte_rawdev_pmd.h\"\n #include \"rte_bus_ifpga.h\"\n@@ -605,6 +607,236 @@\n };\n \n static int\n+ifpga_get_fme_error_prop(struct opae_manager *mgr,\n+\t\tu64 prop_id, u64 *val)\n+{\n+\tstruct feature_prop prop;\n+\n+\tprop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;\n+\tprop.prop_id = prop_id;\n+\n+\tif (opae_manager_ifpga_get_prop(mgr, &prop))\n+\t\treturn -EINVAL;\n+\n+\t*val = prop.data;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ifpga_set_fme_error_prop(struct opae_manager *mgr,\n+\t\tu64 prop_id, u64 val)\n+{\n+\tstruct feature_prop prop;\n+\n+\tprop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;\n+\tprop.prop_id = prop_id;\n+\n+\tprop.data = val;\n+\n+\tif (opae_manager_ifpga_set_prop(mgr, &prop))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int\n+fme_err_read_seu_emr(struct opae_manager *mgr)\n+{\n+\tu64 val;\n+\tint ret;\n+\n+\tret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\tIFPGA_RAWDEV_PMD_INFO(\"seu emr low: 0x%lx\\n\", val);\n+\n+\tret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\tIFPGA_RAWDEV_PMD_INFO(\"seu emr high: 0x%lx\\n\", val);\n+\n+\treturn 0;\n+}\n+\n+static int fme_clear_warning_intr(struct opae_manager *mgr)\n+{\n+\tu64 val;\n+\n+\tif (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))\n+\t\treturn -EINVAL;\n+\n+\tif (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))\n+\t\treturn -EINVAL;\n+\tif ((val & 0x40) != 0)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"clean not done\\n\");\n+\n+\treturn 0;\n+}\n+\n+static int\n+fme_err_handle_error0(struct opae_manager *mgr)\n+{\n+\tstruct feature_fme_error0 fme_error0;\n+\tu64 val;\n+\n+\tif (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))\n+\t\treturn -EINVAL;\n+\n+\tfme_error0.csr = val;\n+\n+\tif (fme_error0.fabric_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Fabric error\\n\");\n+\telse if (fme_error0.fabfifo_overflow)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Fabric fifo under/overflow error\\n\");\n+\telse if (fme_error0.afu_acc_mode_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"AFU PF/VF access mismatch detected\\n\");\n+\telse if (fme_error0.pcie0cdc_parity_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"PCIe0 CDC Parity Error\\n\");\n+\telse if (fme_error0.cvlcdc_parity_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"CVL CDC Parity Error\\n\");\n+\telse if (fme_error0.fpgaseuerr) {\n+\t\tfme_err_read_seu_emr(mgr);\n+\t\trte_panic(\"SEU error occurred\\n\");\n+\t}\n+\n+\t/* clean the errors */\n+\tif (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static int\n+fme_err_handle_catfatal_error(struct opae_manager *mgr)\n+{\n+\tstruct feature_fme_ras_catfaterror fme_catfatal;\n+\tu64 val;\n+\n+\tif (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))\n+\t\treturn -EINVAL;\n+\n+\tfme_catfatal.csr = val;\n+\n+\tif (fme_catfatal.cci_fatal_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"CCI error detected\\n\");\n+\telse if (fme_catfatal.fabric_fatal_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Fabric fatal error detected\\n\");\n+\telse if (fme_catfatal.pcie_poison_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Poison error from PCIe ports\\n\");\n+\telse if (fme_catfatal.inject_fata_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Injected Fatal Error\\n\");\n+\telse if (fme_catfatal.crc_catast_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"a catastrophic EDCRC error\\n\");\n+\telse if (fme_catfatal.injected_catast_err)\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Injected Catastrophic Error\\n\");\n+\telse if (fme_catfatal.bmc_seu_catast_err) {\n+\t\tfme_err_read_seu_emr(mgr);\n+\t\trte_panic(\"SEU error occurred in BMC\\n\");\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+fme_err_handle_nonfaterror(struct opae_manager *mgr)\n+{\n+\tstruct feature_fme_ras_nonfaterror nonfaterr;\n+\tu64 val;\n+\n+\tif (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))\n+\t\treturn -EINVAL;\n+\n+\tnonfaterr.csr = val;\n+\n+\tif (nonfaterr.temp_thresh_ap1)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"Temperature threshold triggered AP1\\n\");\n+\telse if (nonfaterr.temp_thresh_ap2)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"Temperature threshold triggered AP2\\n\");\n+\telse if (nonfaterr.pcie_error)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"an error has occurred in pcie\\n\");\n+\telse if (nonfaterr.portfatal_error)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"fatal error occurred in AFU port.\\n\");\n+\telse if (nonfaterr.proc_hot)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"a ProcHot event\\n\");\n+\telse if (nonfaterr.afu_acc_mode_err)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"an AFU PF/VF access mismatch\\n\");\n+\telse if (nonfaterr.injected_nonfata_err) {\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"Injected Warning Error\\n\");\n+\t\tfme_clear_warning_intr(mgr);\n+\t} else if (nonfaterr.temp_thresh_AP6)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"Temperature threshold triggered AP6\\n\");\n+\telse if (nonfaterr.power_thresh_AP1)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"Power threshold triggered AP1\\n\");\n+\telse if (nonfaterr.power_thresh_AP2)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"Power threshold triggered AP2\\n\");\n+\telse if (nonfaterr.mbp_err)\n+\t\tIFPGA_RAWDEV_PMD_INFO(\"an MBP event\\n\");\n+\n+\treturn 0;\n+}\n+\n+static void\n+fme_interrupt_handler(void *param)\n+{\n+\tstruct opae_manager *mgr = (struct opae_manager *)param;\n+\n+\tIFPGA_RAWDEV_PMD_INFO(\"%s interrupt occurred\\n\", __func__);\n+\n+\tfme_err_handle_error0(mgr);\n+\tfme_err_handle_nonfaterror(mgr);\n+\tfme_err_handle_catfatal_error(mgr);\n+}\n+\n+static struct rte_intr_handle fme_intr_handle;\n+\n+static int ifpga_register_fme_interrupt(struct opae_manager *mgr)\n+{\n+\tint ret;\n+\tstruct fpga_fme_err_irq_set err_irq_set;\n+\n+\tfme_intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;\n+\n+\tret = rte_intr_efd_enable(&fme_intr_handle, 1);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\tfme_intr_handle.fd = fme_intr_handle.efds[0];\n+\n+\tIFPGA_RAWDEV_PMD_DEBUG(\"vfio_dev_fd=%d, efd=%d, fd=%d\\n\",\n+\t\t\tfme_intr_handle.vfio_dev_fd,\n+\t\t\tfme_intr_handle.efds[0], fme_intr_handle.fd);\n+\n+\terr_irq_set.evtfd = fme_intr_handle.efds[0];\n+\tret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\t/* register FME interrupt using DPDK API */\n+\tret = rte_intr_callback_register(&fme_intr_handle,\n+\t\t\tfme_interrupt_handler,\n+\t\t\t(void *)mgr);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\tIFPGA_RAWDEV_PMD_INFO(\"success register fme interrupt\\n\");\n+\n+\treturn 0;\n+}\n+\n+static int\n+ifpga_unregister_fme_interrupt(struct opae_manager *mgr)\n+{\n+\trte_intr_efd_disable(&fme_intr_handle);\n+\n+\treturn rte_intr_callback_unregister(&fme_intr_handle,\n+\t\t\tfme_interrupt_handler,\n+\t\t\t(void *)mgr);\n+}\n+\n+static int\n ifpga_rawdev_create(struct rte_pci_device *pci_dev,\n \t\t\tint socket_id)\n {\n@@ -652,6 +884,7 @@\n \t}\n \tdata->device_id = pci_dev->id.device_id;\n \tdata->vendor_id = pci_dev->id.vendor_id;\n+\tdata->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;\n \n \tadapter = rawdev->dev_private;\n \t/* create a opae_adapter based on above device data */\n@@ -677,6 +910,10 @@\n \t\tIFPGA_RAWDEV_PMD_INFO(\"this is a PF function\");\n \t}\n \n+\tret = ifpga_register_fme_interrupt(mgr);\n+\tif (ret)\n+\t\tgoto free_adapter_data;\n+\n \treturn ret;\n \n free_adapter_data:\n@@ -696,6 +933,7 @@\n \tstruct rte_rawdev *rawdev;\n \tchar name[RTE_RAWDEV_NAME_MAX_LEN];\n \tstruct opae_adapter *adapter;\n+\tstruct opae_manager *mgr;\n \n \tif (!pci_dev) {\n \t\tIFPGA_RAWDEV_PMD_ERR(\"Invalid pci_dev of the device!\");\n@@ -720,6 +958,13 @@\n \tif (!adapter)\n \t\treturn -ENODEV;\n \n+\tmgr = opae_adapter_get_mgr(adapter);\n+\tif (!mgr)\n+\t\treturn -ENODEV;\n+\n+\tif (ifpga_unregister_fme_interrupt(mgr))\n+\t\treturn -EINVAL;\n+\n \topae_adapter_data_free(adapter->data);\n \topae_adapter_free(adapter);\n \n",
    "prefixes": [
        "v8",
        "10/18"
    ]
}