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GET /api/patches/60594/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 60594,
    "url": "http://patches.dpdk.org/api/patches/60594/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191007065155.1756-6-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20191007065155.1756-6-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20191007065155.1756-6-pbhagavatula@marvell.com",
    "date": "2019-10-07T06:51:52",
    "name": "[v9,5/7] drivers/net: update Rx flow flag and mark capabilities",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "7c6003d2828fad6cace0b2a8bd72b7350e557ea3",
    "submitter": {
        "id": 1183,
        "url": "http://patches.dpdk.org/api/people/1183/?format=api",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191007065155.1756-6-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 6715,
            "url": "http://patches.dpdk.org/api/series/6715/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6715",
            "date": "2019-10-07T06:51:47",
            "name": "ethdev: add new Rx offload flags",
            "version": 9,
            "mbox": "http://patches.dpdk.org/series/6715/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/60594/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/60594/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 447511C2B8;\n\tMon,  7 Oct 2019 08:52:43 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 6F43A1C2B6\n\tfor <dev@dpdk.org>; Mon,  7 Oct 2019 08:52:41 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx976oM8E022722; Sun, 6 Oct 2019 23:52:39 -0700",
            "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2verhrddv2-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 06 Oct 2019 23:52:39 -0700",
            "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 6 Oct 2019 23:52:37 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 6 Oct 2019 23:52:37 -0700",
            "from BG-LT7430.marvell.com (unknown [10.28.17.68])\n\tby maili.marvell.com (Postfix) with ESMTP id D80EC3F7040;\n\tSun,  6 Oct 2019 23:52:24 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=V4mfsR+LbAm9m1SpZSYs/mcy44dvLC3/dlcGQeOVx08=;\n\tb=BRRw8bL8VDjREp0+vhiDmunx7nPxVN98h3z+HSdQMtDM6xgSfuswfrrcvnpCgiY/CQ7t\n\tQWGBicTUa+NVcyekEQW2Xj1jQ9dugc8Yt0rpg5n9GvcSSc50MWOPZrbnM3iOQQjhDmlM\n\twQdwBEF0S5a3IIkj8Ku6KxLzhBI9DRsSoNAGSYmclGW7jG6ZO+DR+g1muBHp6jclgwTA\n\t5CmnD6wq2oaObbwnN8Gx+oN4AOMWQLBGRe6rr91pcKr3BcQqBJeUoOiDuZ8QeBrE0Gcr\n\t45rXxa4FESefa4URnUHLZHqylMDkHzQVe+OGlYhaM/ozGkIlJ7YbWf5P4/N1DITZYSB1\n\t2A== ",
        "From": "<pbhagavatula@marvell.com>",
        "To": "<arybchenko@solarflare.com>, <jerinj@marvell.com>, Ajit Khaparde\n\t<ajit.khaparde@broadcom.com>,\n\tSomnath Kotur <somnath.kotur@broadcom.com>, \n\tJohn Daley <johndale@cisco.com>, Hyong Youb Kim <hyonkim@cisco.com>, \n\t\"Beilei Xing\" <beilei.xing@intel.com>,\n\tQi Zhang <qi.z.zhang@intel.com>, Jingjing Wu <jingjing.wu@intel.com>, \n\tWenzhuo Lu <wenzhuo.lu@intel.com>, Qiming Yang <qiming.yang@intel.com>,\n\tKonstantin Ananyev <konstantin.ananyev@intel.com>,\n\tMatan Azrad <matan@mellanox.com>, Shahaf Shuler <shahafs@mellanox.com>,\n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>",
        "CC": "<dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>",
        "Date": "Mon, 7 Oct 2019 12:21:52 +0530",
        "Message-ID": "<20191007065155.1756-6-pbhagavatula@marvell.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20191007065155.1756-1-pbhagavatula@marvell.com>",
        "References": "<20191002213612.14207-1-pbhagavatula@marvell.com>\n\t<20191007065155.1756-1-pbhagavatula@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-10-07_01:2019-10-03,2019-10-07 signatures=0",
        "Subject": "[dpdk-dev] [PATCH v9 5/7] drivers/net: update Rx flow flag and mark\n\tcapabilities",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd DEV_RX_OFFLOAD_FLOW_MARK flag for all PMDs that support flow action\nflag and mark.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nReviewed-by: Andrew Rybchenko <arybchenko@solarflare.com>\nAcked-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/net/bnxt/bnxt_ethdev.c          | 3 ++-\n drivers/net/enic/enic_res.c             | 3 ++-\n drivers/net/i40e/i40e_ethdev.c          | 3 ++-\n drivers/net/iavf/iavf_ethdev.c          | 3 ++-\n drivers/net/ice/ice_ethdev.c            | 3 ++-\n drivers/net/ixgbe/ixgbe_rxtx.c          | 3 ++-\n drivers/net/mlx5/mlx5_rxq.c             | 3 ++-\n drivers/net/octeontx2/otx2_ethdev.h     | 3 ++-\n drivers/net/octeontx2/otx2_flow.c       | 9 ++-------\n drivers/net/octeontx2/otx2_flow.h       | 1 -\n drivers/net/octeontx2/otx2_flow_parse.c | 5 +----\n drivers/net/sfc/sfc_ef10_essb_rx.c      | 3 ++-\n 12 files changed, 21 insertions(+), 21 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex 6c106baf7..fd1fb7eda 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -161,7 +161,8 @@ static const struct rte_pci_id bnxt_pci_id_map[] = {\n \t\t\t\t     DEV_RX_OFFLOAD_JUMBO_FRAME | \\\n \t\t\t\t     DEV_RX_OFFLOAD_KEEP_CRC | \\\n \t\t\t\t     DEV_RX_OFFLOAD_TCP_LRO | \\\n-\t\t\t\t     DEV_RX_OFFLOAD_RSS_HASH)\n+\t\t\t\t     DEV_RX_OFFLOAD_RSS_HASH | \\\n+\t\t\t\t     DEV_RX_OFFLOAD_FLOW_MARK)\n \n static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);\n static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);\ndiff --git a/drivers/net/enic/enic_res.c b/drivers/net/enic/enic_res.c\nindex 607a085f8..3503d5d7e 100644\n--- a/drivers/net/enic/enic_res.c\n+++ b/drivers/net/enic/enic_res.c\n@@ -199,7 +199,8 @@ int enic_get_vnic_config(struct enic *enic)\n \t\tDEV_RX_OFFLOAD_IPV4_CKSUM |\n \t\tDEV_RX_OFFLOAD_UDP_CKSUM |\n \t\tDEV_RX_OFFLOAD_TCP_CKSUM |\n-\t\tDEV_RX_OFFLOAD_RSS_HASH;\n+\t\tDEV_RX_OFFLOAD_RSS_HASH |\n+\t\tDEV_RX_OFFLOAD_FLOW_MARK;\n \tenic->tx_offload_mask =\n \t\tPKT_TX_IPV6 |\n \t\tPKT_TX_IPV4 |\ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 7058e0213..6311943be 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -3512,7 +3512,8 @@ i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\tDEV_RX_OFFLOAD_VLAN_EXTEND |\n \t\tDEV_RX_OFFLOAD_VLAN_FILTER |\n \t\tDEV_RX_OFFLOAD_JUMBO_FRAME |\n-\t\tDEV_RX_OFFLOAD_RSS_HASH;\n+\t\tDEV_RX_OFFLOAD_RSS_HASH |\n+\t\tDEV_RX_OFFLOAD_FLOW_MARK;\n \n \tdev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;\n \tdev_info->tx_offload_capa =\ndiff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c\nindex aef91a79b..7bdaa87b1 100644\n--- a/drivers/net/iavf/iavf_ethdev.c\n+++ b/drivers/net/iavf/iavf_ethdev.c\n@@ -518,7 +518,8 @@ iavf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\tDEV_RX_OFFLOAD_SCATTER |\n \t\tDEV_RX_OFFLOAD_JUMBO_FRAME |\n \t\tDEV_RX_OFFLOAD_VLAN_FILTER |\n-\t\tDEV_RX_OFFLOAD_RSS_HASH;\n+\t\tDEV_RX_OFFLOAD_RSS_HASH |\n+\t\tDEV_RX_OFFLOAD_FLOW_MARK;\n \tdev_info->tx_offload_capa =\n \t\tDEV_TX_OFFLOAD_VLAN_INSERT |\n \t\tDEV_TX_OFFLOAD_QINQ_INSERT |\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 2e2a6b2af..984af659f 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -2146,7 +2146,8 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\t\tDEV_RX_OFFLOAD_QINQ_STRIP |\n \t\t\tDEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |\n \t\t\tDEV_RX_OFFLOAD_VLAN_EXTEND |\n-\t\t\tDEV_RX_OFFLOAD_RSS_HASH;\n+\t\t\tDEV_RX_OFFLOAD_RSS_HASH |\n+\t\t\tDEV_RX_OFFLOAD_FLOW_MARK;\n \t\tdev_info->tx_offload_capa |=\n \t\t\tDEV_TX_OFFLOAD_QINQ_INSERT |\n \t\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex fa572d184..1481e2426 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -2873,7 +2873,8 @@ ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev)\n \t\t   DEV_RX_OFFLOAD_JUMBO_FRAME |\n \t\t   DEV_RX_OFFLOAD_VLAN_FILTER |\n \t\t   DEV_RX_OFFLOAD_SCATTER |\n-\t\t   DEV_RX_OFFLOAD_RSS_HASH;\n+\t\t   DEV_RX_OFFLOAD_RSS_HASH |\n+\t\t   DEV_RX_OFFLOAD_FLOW_MARK;\n \n \tif (hw->mac.type == ixgbe_mac_82598EB)\n \t\toffloads |= DEV_RX_OFFLOAD_VLAN_STRIP;\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex b5fd57693..1bf01bda3 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -369,7 +369,8 @@ mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev)\n \tuint64_t offloads = (DEV_RX_OFFLOAD_SCATTER |\n \t\t\t     DEV_RX_OFFLOAD_TIMESTAMP |\n \t\t\t     DEV_RX_OFFLOAD_JUMBO_FRAME |\n-\t\t\t     DEV_RX_OFFLOAD_RSS_HASH);\n+\t\t\t     DEV_RX_OFFLOAD_RSS_HASH |\n+\t\t\t     DEV_RX_OFFLOAD_FLOW_MARK);\n \n \tif (config->hw_fcs_strip)\n \t\toffloads |= DEV_RX_OFFLOAD_KEEP_CRC;\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 0cca6746d..97c1a636a 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -141,7 +141,8 @@\n \tDEV_RX_OFFLOAD_VLAN_FILTER\t| \\\n \tDEV_RX_OFFLOAD_QINQ_STRIP\t| \\\n \tDEV_RX_OFFLOAD_TIMESTAMP\t| \\\n-\tDEV_RX_OFFLOAD_RSS_HASH)\n+\tDEV_RX_OFFLOAD_RSS_HASH\t\t| \\\n+\tDEV_RX_OFFLOAD_FLOW_MARK)\n \n #define NIX_DEFAULT_RSS_CTX_GROUP  0\n #define NIX_DEFAULT_RSS_MCAM_IDX  -1\ndiff --git a/drivers/net/octeontx2/otx2_flow.c b/drivers/net/octeontx2/otx2_flow.c\nindex bdbf123a9..ea4e380b1 100644\n--- a/drivers/net/octeontx2/otx2_flow.c\n+++ b/drivers/net/octeontx2/otx2_flow.c\n@@ -524,11 +524,8 @@ otx2_flow_destroy(struct rte_eth_dev *dev,\n \t\tNIX_RX_ACT_MATCH_MASK;\n \n \tif (match_id && match_id < OTX2_FLOW_ACTION_FLAG_DEFAULT) {\n-\t\tif (rte_atomic32_read(&npc->mark_actions) == 0)\n-\t\t\treturn -EINVAL;\n-\n-\t\t/* Clear mark offload flag if there are no more mark actions */\n-\t\tif (rte_atomic32_sub_return(&npc->mark_actions, 1) == 0) {\n+\t\t/* Clear mark offload flag if there is no more mark action */\n+\t\tif (hw->rx_offloads & DEV_RX_OFFLOAD_FLOW_MARK) {\n \t\t\thw->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;\n \t\t\totx2_eth_set_rx_function(dev);\n \t\t}\n@@ -821,8 +818,6 @@ otx2_flow_init(struct otx2_eth_dev *hw)\n \t\treturn rc;\n \t}\n \n-\trte_atomic32_init(&npc->mark_actions);\n-\n \tnpc->mcam_entries = NPC_MCAM_TOT_ENTRIES >> npc->keyw[NPC_MCAM_RX];\n \t/* Free, free_rev, live and live_rev entries */\n \tbmap_sz = rte_bitmap_get_memory_footprint(npc->mcam_entries);\ndiff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h\nindex ab068b088..85129cc9d 100644\n--- a/drivers/net/octeontx2/otx2_flow.h\n+++ b/drivers/net/octeontx2/otx2_flow.h\n@@ -160,7 +160,6 @@ TAILQ_HEAD(otx2_flow_list, rte_flow);\n \n /* Accessed from ethdev private - otx2_eth_dev */\n struct otx2_npc_flow_info {\n-\trte_atomic32_t mark_actions;\n \tuint32_t keyx_supp_nmask[NPC_MAX_INTF];/* nibble mask */\n \tuint32_t keyx_len[NPC_MAX_INTF];\t/* per intf key len in bits */\n \tuint32_t datax_len[NPC_MAX_INTF];\t/* per intf data len in bits */\ndiff --git a/drivers/net/octeontx2/otx2_flow_parse.c b/drivers/net/octeontx2/otx2_flow_parse.c\nindex 6670c1a70..541479445 100644\n--- a/drivers/net/octeontx2/otx2_flow_parse.c\n+++ b/drivers/net/octeontx2/otx2_flow_parse.c\n@@ -761,7 +761,6 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev,\n \t\t\tstruct rte_flow *flow)\n {\n \tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tstruct otx2_npc_flow_info *npc = &hw->npc_flow;\n \tconst struct rte_flow_action_count *act_count;\n \tconst struct rte_flow_action_mark *act_mark;\n \tconst struct rte_flow_action_queue *act_q;\n@@ -795,13 +794,11 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev,\n \t\t\t}\n \t\t\tmark = act_mark->id + 1;\n \t\t\treq_act |= OTX2_FLOW_ACT_MARK;\n-\t\t\trte_atomic32_inc(&npc->mark_actions);\n \t\t\tbreak;\n \n \t\tcase RTE_FLOW_ACTION_TYPE_FLAG:\n \t\t\tmark = OTX2_FLOW_FLAG_VAL;\n \t\t\treq_act |= OTX2_FLOW_ACT_FLAG;\n-\t\t\trte_atomic32_inc(&npc->mark_actions);\n \t\t\tbreak;\n \n \t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n@@ -979,7 +976,7 @@ otx2_flow_parse_actions(struct rte_eth_dev *dev,\n \tif (mark)\n \t\tflow->npc_action |= (uint64_t)mark << 40;\n \n-\tif (rte_atomic32_read(&npc->mark_actions) == 1) {\n+\tif (hw->rx_offloads & DEV_RX_OFFLOAD_FLOW_MARK) {\n \t\thw->rx_offload_flags |=\n \t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F;\n \t\totx2_eth_set_rx_function(dev);\ndiff --git a/drivers/net/sfc/sfc_ef10_essb_rx.c b/drivers/net/sfc/sfc_ef10_essb_rx.c\nindex 220ef0e47..1887731e2 100644\n--- a/drivers/net/sfc/sfc_ef10_essb_rx.c\n+++ b/drivers/net/sfc/sfc_ef10_essb_rx.c\n@@ -716,7 +716,8 @@ struct sfc_dp_rx sfc_ef10_essb_rx = {\n \t.features\t\t= SFC_DP_RX_FEAT_FLOW_FLAG |\n \t\t\t\t  SFC_DP_RX_FEAT_FLOW_MARK,\n \t.dev_offload_capa\t= DEV_RX_OFFLOAD_CHECKSUM,\n-\t.queue_offload_capa\t= DEV_RX_OFFLOAD_RSS_HASH,\n+\t.queue_offload_capa\t= DEV_RX_OFFLOAD_RSS_HASH |\n+\t\t\t\t  DEV_RX_OFFLOAD_FLOW_MARK,\n \t.get_dev_info\t\t= sfc_ef10_essb_rx_get_dev_info,\n \t.pool_ops_supported\t= sfc_ef10_essb_rx_pool_ops_supported,\n \t.qsize_up_rings\t\t= sfc_ef10_essb_rx_qsize_up_rings,\n",
    "prefixes": [
        "v9",
        "5/7"
    ]
}