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GET /api/patches/60283/?format=api
{ "id": 60283, "url": "http://patches.dpdk.org/api/patches/60283/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20191001064048.5624-4-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20191001064048.5624-4-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20191001064048.5624-4-rnagadheeraj@marvell.com", "date": "2019-10-01T06:41:25", "name": "[v7,3/8] crypto/nitrox: add software queue management functionality", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "858dacacb47b3c1d15969563ebb15a9ec96da67a", "submitter": { "id": 1365, "url": "http://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20191001064048.5624-4-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 6638, "url": "http://patches.dpdk.org/api/series/6638/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6638", "date": "2019-10-01T06:41:18", "name": "add Nitrox crypto device support", "version": 7, "mbox": "http://patches.dpdk.org/series/6638/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/60283/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/60283/checks/", "tags": {}, "related": [], "headers": { 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"XmYQv093WmWMRtIyTfGvTKKF9MvdF8g6bJ3yP6SGR/595NjfbuEqddWlg7YWEc8qCfj+fzd9uRwvctCRxLr3WCrCLTRa8txGHfSyvig6ZgM=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR18MB3375", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-10-01_03:2019-09-30,2019-10-01 signatures=0", "Subject": "[dpdk-dev] [PATCH v7 3/8] crypto/nitrox: add software queue\n\tmanagement functionality", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add software queue management code corresponding to queue pair setup\nand release functions.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n drivers/crypto/nitrox/Makefile | 2 +\n drivers/crypto/nitrox/meson.build | 2 +\n drivers/crypto/nitrox/nitrox_qp.c | 74 +++++++++++++++++\n drivers/crypto/nitrox/nitrox_qp.h | 40 +++++++++\n drivers/crypto/nitrox/nitrox_sym.c | 131 ++++++++++++++++++++++++++++--\n drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 56 +++++++++++++\n drivers/crypto/nitrox/nitrox_sym_reqmgr.h | 13 +++\n 7 files changed, 311 insertions(+), 7 deletions(-)\n create mode 100644 drivers/crypto/nitrox/nitrox_qp.c\n create mode 100644 drivers/crypto/nitrox/nitrox_qp.h\n create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n create mode 100644 drivers/crypto/nitrox/nitrox_sym_reqmgr.h", "diff": "diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile\nindex 06c96ccd7..72530ee1d 100644\n--- a/drivers/crypto/nitrox/Makefile\n+++ b/drivers/crypto/nitrox/Makefile\n@@ -27,5 +27,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_reqmgr.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_qp.c\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build\nindex 1277cf58e..06e006e24 100644\n--- a/drivers/crypto/nitrox/meson.build\n+++ b/drivers/crypto/nitrox/meson.build\n@@ -13,4 +13,6 @@ sources = files(\n \t\t'nitrox_hal.c',\n \t\t'nitrox_logs.c',\n \t\t'nitrox_sym.c',\n+\t\t'nitrox_sym_reqmgr.c',\n+\t\t'nitrox_qp.c'\n \t\t)\ndiff --git a/drivers/crypto/nitrox/nitrox_qp.c b/drivers/crypto/nitrox/nitrox_qp.c\nnew file mode 100644\nindex 000000000..9673bb4f3\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_qp.c\n@@ -0,0 +1,74 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <rte_malloc.h>\n+\n+#include \"nitrox_qp.h\"\n+#include \"nitrox_hal.h\"\n+#include \"nitrox_logs.h\"\n+\n+#define MAX_CMD_QLEN 16384\n+\n+static int\n+nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id)\n+{\n+\tsize_t ridq_size = qp->count * sizeof(*qp->ridq);\n+\n+\tqp->ridq = rte_zmalloc_socket(\"nitrox ridq\", ridq_size,\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t socket_id);\n+\tif (!qp->ridq) {\n+\t\tNITROX_LOG(ERR, \"Failed to create rid queue\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,\n+\t\tuint32_t nb_descriptors, uint8_t instr_size, int socket_id)\n+{\n+\tint err;\n+\tuint32_t count;\n+\n+\tRTE_SET_USED(bar_addr);\n+\tRTE_SET_USED(instr_size);\n+\tcount = rte_align32pow2(nb_descriptors);\n+\tif (count > MAX_CMD_QLEN) {\n+\t\tNITROX_LOG(ERR, \"%s: Number of descriptors too big %d,\"\n+\t\t\t \" greater than max queue length %d\\n\",\n+\t\t\t dev_name, count,\n+\t\t\t MAX_CMD_QLEN);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tqp->count = count;\n+\tqp->head = qp->tail = 0;\n+\trte_atomic16_init(&qp->pending_count);\n+\terr = nitrox_setup_ridq(qp, socket_id);\n+\tif (err)\n+\t\tgoto ridq_err;\n+\n+\treturn 0;\n+\n+ridq_err:\n+\treturn err;\n+\n+}\n+\n+static void\n+nitrox_release_ridq(struct nitrox_qp *qp)\n+{\n+\trte_free(qp->ridq);\n+}\n+\n+int\n+nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr)\n+{\n+\tRTE_SET_USED(bar_addr);\n+\tnitrox_release_ridq(qp);\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/nitrox/nitrox_qp.h b/drivers/crypto/nitrox/nitrox_qp.h\nnew file mode 100644\nindex 000000000..cf0102ff9\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_qp.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_QP_H_\n+#define _NITROX_QP_H_\n+\n+#include <stdbool.h>\n+\n+#include <rte_io.h>\n+\n+struct nitrox_softreq;\n+\n+struct rid {\n+\tstruct nitrox_softreq *sr;\n+};\n+\n+struct nitrox_qp {\n+\tstruct rid *ridq;\n+\tuint32_t count;\n+\tuint32_t head;\n+\tuint32_t tail;\n+\tstruct rte_mempool *sr_mp;\n+\tstruct rte_cryptodev_stats stats;\n+\tuint16_t qno;\n+\trte_atomic16_t pending_count;\n+};\n+\n+static inline bool\n+nitrox_qp_is_empty(struct nitrox_qp *qp)\n+{\n+\treturn (rte_atomic16_read(&qp->pending_count) == 0);\n+}\n+\n+int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr,\n+\t\t const char *dev_name, uint32_t nb_descriptors,\n+\t\t uint8_t inst_size, int socket_id);\n+int nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr);\n+\n+#endif /* _NITROX_QP_H_ */\ndiff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/nitrox_sym.c\nindex 12817c6c7..0ac490829 100644\n--- a/drivers/crypto/nitrox/nitrox_sym.c\n+++ b/drivers/crypto/nitrox/nitrox_sym.c\n@@ -9,9 +9,12 @@\n \n #include \"nitrox_sym.h\"\n #include \"nitrox_device.h\"\n+#include \"nitrox_qp.h\"\n+#include \"nitrox_sym_reqmgr.h\"\n #include \"nitrox_logs.h\"\n \n #define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox_sym\n+#define NPS_PKT_IN_INSTR_SIZE 64\n \n struct nitrox_sym_device {\n \tstruct rte_cryptodev *cdev;\n@@ -89,12 +92,126 @@ nitrox_sym_dev_info_get(struct rte_cryptodev *cdev,\n \tinfo->sym.max_nb_sessions = 0;\n }\n \n+static void\n+nitrox_sym_dev_stats_get(struct rte_cryptodev *cdev,\n+\t\t\t struct rte_cryptodev_stats *stats)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct nitrox_qp *qp = cdev->data->queue_pairs[qp_id];\n+\n+\t\tif (!qp)\n+\t\t\tcontinue;\n+\n+\t\tstats->enqueued_count += qp->stats.enqueued_count;\n+\t\tstats->dequeued_count += qp->stats.dequeued_count;\n+\t\tstats->enqueue_err_count += qp->stats.enqueue_err_count;\n+\t\tstats->dequeue_err_count += qp->stats.dequeue_err_count;\n+\t}\n+}\n+\n+static void\n+nitrox_sym_dev_stats_reset(struct rte_cryptodev *cdev)\n+{\n+\tint qp_id;\n+\n+\tfor (qp_id = 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) {\n+\t\tstruct nitrox_qp *qp = cdev->data->queue_pairs[qp_id];\n+\n+\t\tif (!qp)\n+\t\t\tcontinue;\n+\n+\t\tmemset(&qp->stats, 0, sizeof(qp->stats));\n+\t}\n+}\n+\n static int\n-nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id)\n+nitrox_sym_dev_qp_setup(struct rte_cryptodev *cdev, uint16_t qp_id,\n+\t\t\tconst struct rte_cryptodev_qp_conf *qp_conf,\n+\t\t\tint socket_id)\n {\n-\tRTE_SET_USED(cdev);\n-\tRTE_SET_USED(qp_id);\n+\tstruct nitrox_sym_device *sym_dev = cdev->data->dev_private;\n+\tstruct nitrox_device *ndev = sym_dev->ndev;\n+\tstruct nitrox_qp *qp = NULL;\n+\tint err;\n+\n+\tNITROX_LOG(DEBUG, \"queue %d\\n\", qp_id);\n+\tif (qp_id >= ndev->nr_queues) {\n+\t\tNITROX_LOG(ERR, \"queue %u invalid, max queues supported %d\\n\",\n+\t\t\t qp_id, ndev->nr_queues);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (cdev->data->queue_pairs[qp_id]) {\n+\t\terr = nitrox_sym_dev_qp_release(cdev, qp_id);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\tqp = rte_zmalloc_socket(\"nitrox PMD qp\", sizeof(*qp),\n+\t\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\t\tsocket_id);\n+\tif (!qp) {\n+\t\tNITROX_LOG(ERR, \"Failed to allocate nitrox qp\\n\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tqp->qno = qp_id;\n+\terr = nitrox_qp_setup(qp, ndev->bar_addr, cdev->data->name,\n+\t\t\t qp_conf->nb_descriptors, NPS_PKT_IN_INSTR_SIZE,\n+\t\t\t socket_id);\n+\tif (unlikely(err))\n+\t\tgoto qp_setup_err;\n+\n+\tqp->sr_mp = nitrox_sym_req_pool_create(cdev, qp->count, qp_id,\n+\t\t\t\t\t socket_id);\n+\tif (unlikely(!qp->sr_mp))\n+\t\tgoto req_pool_err;\n+\n+\tcdev->data->queue_pairs[qp_id] = qp;\n+\tNITROX_LOG(DEBUG, \"queue %d setup done\\n\", qp_id);\n \treturn 0;\n+\n+req_pool_err:\n+\tnitrox_qp_release(qp, ndev->bar_addr);\n+qp_setup_err:\n+\trte_free(qp);\n+\treturn err;\n+}\n+\n+static int\n+nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id)\n+{\n+\tstruct nitrox_sym_device *sym_dev = cdev->data->dev_private;\n+\tstruct nitrox_device *ndev = sym_dev->ndev;\n+\tstruct nitrox_qp *qp;\n+\tint err;\n+\n+\tNITROX_LOG(DEBUG, \"queue %d\\n\", qp_id);\n+\tif (qp_id >= ndev->nr_queues) {\n+\t\tNITROX_LOG(ERR, \"queue %u invalid, max queues supported %d\\n\",\n+\t\t\t qp_id, ndev->nr_queues);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tqp = cdev->data->queue_pairs[qp_id];\n+\tif (!qp) {\n+\t\tNITROX_LOG(DEBUG, \"queue %u already freed\\n\", qp_id);\n+\t\treturn 0;\n+\t}\n+\n+\tif (!nitrox_qp_is_empty(qp)) {\n+\t\tNITROX_LOG(ERR, \"queue %d not empty\\n\", qp_id);\n+\t\treturn -EAGAIN;\n+\t}\n+\n+\tcdev->data->queue_pairs[qp_id] = NULL;\n+\terr = nitrox_qp_release(qp, ndev->bar_addr);\n+\tnitrox_sym_req_pool_free(qp->sr_mp);\n+\trte_free(qp);\n+\tNITROX_LOG(DEBUG, \"queue %d release done\\n\", qp_id);\n+\treturn err;\n }\n \n static struct rte_cryptodev_ops nitrox_cryptodev_ops = {\n@@ -103,10 +220,10 @@ static struct rte_cryptodev_ops nitrox_cryptodev_ops = {\n \t.dev_stop\t\t= nitrox_sym_dev_stop,\n \t.dev_close\t\t= nitrox_sym_dev_close,\n \t.dev_infos_get\t\t= nitrox_sym_dev_info_get,\n-\t.stats_get\t\t= NULL,\n-\t.stats_reset\t\t= NULL,\n-\t.queue_pair_setup\t= NULL,\n-\t.queue_pair_release = NULL,\n+\t.stats_get\t\t= nitrox_sym_dev_stats_get,\n+\t.stats_reset\t\t= nitrox_sym_dev_stats_reset,\n+\t.queue_pair_setup\t= nitrox_sym_dev_qp_setup,\n+\t.queue_pair_release = nitrox_sym_dev_qp_release,\n \t.sym_session_get_size = NULL,\n \t.sym_session_configure = NULL,\n \t.sym_session_clear = NULL\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\nnew file mode 100644\nindex 000000000..42d67317c\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n@@ -0,0 +1,56 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#include <rte_errno.h>\n+\n+#include \"nitrox_sym_reqmgr.h\"\n+#include \"nitrox_logs.h\"\n+\n+struct nitrox_softreq {\n+\trte_iova_t iova;\n+};\n+\n+static void\n+softreq_init(struct nitrox_softreq *sr, rte_iova_t iova)\n+{\n+\tmemset(sr, 0, sizeof(*sr));\n+\tsr->iova = iova;\n+}\n+\n+static void\n+req_pool_obj_init(__rte_unused struct rte_mempool *mp,\n+\t\t __rte_unused void *opaque, void *obj,\n+\t\t __rte_unused unsigned int obj_idx)\n+{\n+\tsoftreq_init(obj, rte_mempool_virt2iova(obj));\n+}\n+\n+struct rte_mempool *\n+nitrox_sym_req_pool_create(struct rte_cryptodev *cdev, uint32_t nobjs,\n+\t\t\t uint16_t qp_id, int socket_id)\n+{\n+\tchar softreq_pool_name[RTE_RING_NAMESIZE];\n+\tstruct rte_mempool *mp;\n+\n+\tsnprintf(softreq_pool_name, RTE_RING_NAMESIZE, \"%s_sr_%d\",\n+\t\t cdev->data->name, qp_id);\n+\tmp = rte_mempool_create(softreq_pool_name,\n+\t\t\t\tRTE_ALIGN_MUL_CEIL(nobjs, 64),\n+\t\t\t\tsizeof(struct nitrox_softreq),\n+\t\t\t\t64, 0, NULL, NULL, req_pool_obj_init, NULL,\n+\t\t\t\tsocket_id, 0);\n+\tif (unlikely(!mp))\n+\t\tNITROX_LOG(ERR, \"Failed to create req pool, qid %d, err %d\\n\",\n+\t\t\t qp_id, rte_errno);\n+\n+\treturn mp;\n+}\n+\n+void\n+nitrox_sym_req_pool_free(struct rte_mempool *mp)\n+{\n+\trte_mempool_free(mp);\n+}\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h\nnew file mode 100644\nindex 000000000..5953c958c\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_SYM_REQMGR_H_\n+#define _NITROX_SYM_REQMGR_H_\n+\n+struct rte_mempool *nitrox_sym_req_pool_create(struct rte_cryptodev *cdev,\n+\t\t\t\t\t uint32_t nobjs, uint16_t qp_id,\n+\t\t\t\t\t int socket_id);\n+void nitrox_sym_req_pool_free(struct rte_mempool *mp);\n+\n+#endif /* _NITROX_SYM_REQMGR_H_ */\n", "prefixes": [ "v7", "3/8" ] }