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GET /api/patches/59823/?format=api
{ "id": 59823, "url": "http://patches.dpdk.org/api/patches/59823/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190926085232.47667-3-jasvinder.singh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190926085232.47667-3-jasvinder.singh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190926085232.47667-3-jasvinder.singh@intel.com", "date": "2019-09-26T08:52:19", "name": "[v3,02/15] sched: modify internal structs for config flexibility", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ab1b221b0b1f4d100127367ff50b559afac8efc6", "submitter": { "id": 285, "url": "http://patches.dpdk.org/api/people/285/?format=api", "name": "Jasvinder Singh", "email": "jasvinder.singh@intel.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190926085232.47667-3-jasvinder.singh@intel.com/mbox/", "series": [ { "id": 6540, "url": "http://patches.dpdk.org/api/series/6540/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6540", "date": "2019-09-26T08:52:17", "name": "sched: subport level configuration of pipe nodes", "version": 3, "mbox": "http://patches.dpdk.org/series/6540/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/59823/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/59823/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9B7021BF2F;\n\tThu, 26 Sep 2019 10:52:50 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id EA7C51BEE4\n\tfor <dev@dpdk.org>; Thu, 26 Sep 2019 10:52:44 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Sep 2019 01:52:44 -0700", "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby fmsmga007.fm.intel.com with ESMTP; 26 Sep 2019 01:52:43 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,551,1559545200\"; d=\"scan'208\";a=\"189945545\"", "From": "Jasvinder Singh <jasvinder.singh@intel.com>", "To": "dev@dpdk.org", "Cc": "cristian.dumitrescu@intel.com,\n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>", "Date": "Thu, 26 Sep 2019 09:52:19 +0100", "Message-Id": "<20190926085232.47667-3-jasvinder.singh@intel.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190926085232.47667-1-jasvinder.singh@intel.com>", "References": "<20190909100530.86020-1-jasvinder.singh@intel.com>\n\t<20190926085232.47667-1-jasvinder.singh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 02/15] sched: modify internal structs for\n\tconfig flexibility", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update internal structures related to port and subport to allow\ndifferent subports of the same port to have different configuration\nin terms of number of pipes, pipe queue sizes, etc.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 106 ++++++++++++++++++++++++++---------\n 1 file changed, 78 insertions(+), 28 deletions(-)", "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex d8ab21d64..672412b77 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -47,33 +47,6 @@\n */\n #define RTE_SCHED_TIME_SHIFT\t\t 8\n \n-struct rte_sched_subport {\n-\t/* Token bucket (TB) */\n-\tuint64_t tb_time; /* time of last update */\n-\tuint32_t tb_period;\n-\tuint32_t tb_credits_per_period;\n-\tuint32_t tb_size;\n-\tuint32_t tb_credits;\n-\n-\t/* Traffic classes (TCs) */\n-\tuint64_t tc_time; /* time of next update */\n-\tuint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint32_t tc_period;\n-\n-\t/* TC oversubscription */\n-\tuint32_t tc_ov_wm;\n-\tuint32_t tc_ov_wm_min;\n-\tuint32_t tc_ov_wm_max;\n-\tuint8_t tc_ov_period_id;\n-\tuint8_t tc_ov;\n-\tuint32_t tc_ov_n;\n-\tdouble tc_ov_rate;\n-\n-\t/* Statistics */\n-\tstruct rte_sched_subport_stats stats;\n-};\n-\n struct rte_sched_pipe_profile {\n \t/* Token bucket (TB) */\n \tuint32_t tb_period;\n@@ -107,7 +80,6 @@ struct rte_sched_pipe {\n \t/* TC oversubscription */\n \tuint32_t tc_ov_credits;\n \tuint8_t tc_ov_period_id;\n-\tuint8_t reserved[3];\n } __rte_cache_aligned;\n \n struct rte_sched_queue {\n@@ -166,6 +138,72 @@ struct rte_sched_grinder {\n \tuint8_t wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];\n };\n \n+struct rte_sched_subport {\n+\t/* Token bucket (TB) */\n+\tuint64_t tb_time; /* time of last update */\n+\tuint32_t tb_period;\n+\tuint32_t tb_credits_per_period;\n+\tuint32_t tb_size;\n+\tuint32_t tb_credits;\n+\n+\t/* Traffic classes (TCs) */\n+\tuint64_t tc_time; /* time of next update */\n+\tuint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n+\tuint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n+\tuint32_t tc_period;\n+\n+\t/* TC oversubscription */\n+\tuint32_t tc_ov_wm;\n+\tuint32_t tc_ov_wm_min;\n+\tuint32_t tc_ov_wm_max;\n+\tuint8_t tc_ov_period_id;\n+\tuint8_t tc_ov;\n+\tuint32_t tc_ov_n;\n+\tdouble tc_ov_rate;\n+\n+\t/* Statistics */\n+\tstruct rte_sched_subport_stats stats;\n+\n+\t/* Subport pipes */\n+\tuint32_t n_pipes_per_subport_enabled;\n+\tuint32_t n_pipe_profiles;\n+\tuint32_t n_max_pipe_profiles;\n+\n+\t/* Pipe best-effort TC rate */\n+\tuint32_t pipe_tc_be_rate_max;\n+\n+\t/* Pipe queues size */\n+\tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n+\n+#ifdef RTE_SCHED_RED\n+\tstruct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];\n+#endif\n+\n+\t/* Scheduling loop detection */\n+\tuint32_t pipe_loop;\n+\tuint32_t pipe_exhaustion;\n+\n+\t/* Bitmap */\n+\tstruct rte_bitmap *bmp;\n+\tuint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;\n+\n+\t/* Grinders */\n+\tstruct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];\n+\tuint32_t busy_grinders;\n+\n+\t/* Queue base calculation */\n+\tuint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];\n+\tuint32_t qsize_sum;\n+\n+\tstruct rte_sched_pipe *pipe;\n+\tstruct rte_sched_queue *queue;\n+\tstruct rte_sched_queue_extra *queue_extra;\n+\tstruct rte_sched_pipe_profile *pipe_profiles;\n+\tuint8_t *bmp_array;\n+\tstruct rte_mbuf **queue_array;\n+\tuint8_t memory[0] __rte_cache_aligned;\n+} __rte_cache_aligned;\n+\n struct rte_sched_port {\n \t/* User parameters */\n \tuint32_t n_subports_per_port;\n@@ -177,6 +215,7 @@ struct rte_sched_port {\n \tuint32_t rate;\n \tuint32_t mtu;\n \tuint32_t frame_overhead;\n+\tint socket;\n \tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \tuint32_t n_pipe_profiles;\n \tuint32_t n_max_pipe_profiles;\n@@ -210,6 +249,7 @@ struct rte_sched_port {\n \tuint32_t qsize_sum;\n \n \t/* Large data structures */\n+\tstruct rte_sched_subport *subports[0];\n \tstruct rte_sched_subport *subport;\n \tstruct rte_sched_pipe *pipe;\n \tstruct rte_sched_queue *queue;\n@@ -231,6 +271,16 @@ enum rte_sched_port_array {\n \te_RTE_SCHED_PORT_ARRAY_TOTAL,\n };\n \n+enum rte_sched_subport_array {\n+\te_RTE_SCHED_SUBPORT_ARRAY_PIPE = 0,\n+\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE,\n+\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_EXTRA,\n+\te_RTE_SCHED_SUBPORT_ARRAY_PIPE_PROFILES,\n+\te_RTE_SCHED_SUBPORT_ARRAY_BMP_ARRAY,\n+\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY,\n+\te_RTE_SCHED_SUBPORT_ARRAY_TOTAL,\n+};\n+\n #ifdef RTE_SCHED_COLLECT_STATS\n \n static inline uint32_t\n", "prefixes": [ "v3", "02/15" ] }