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GET /api/patches/58296/?format=api
{ "id": 58296, "url": "http://patches.dpdk.org/api/patches/58296/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1567146501-8224-10-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567146501-8224-10-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567146501-8224-10-git-send-email-anoobj@marvell.com", "date": "2019-08-30T06:28:19", "name": "[09/11] crypto/octeontx2: add dequeue burst", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "848b6164211f48d0be5768f5c8a347e970dd99ab", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1567146501-8224-10-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 6176, "url": "http://patches.dpdk.org/api/series/6176/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6176", "date": "2019-08-30T06:28:10", "name": "add OCTEON TX2 crypto PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/6176/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/58296/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/58296/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 87ADD1E86E;\n\tFri, 30 Aug 2019 08:32:41 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 444F81E86E\n\tfor <dev@dpdk.org>; Fri, 30 Aug 2019 08:32:40 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx7U6ULNB000551; Thu, 29 Aug 2019 23:32:39 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2upmepj41m-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 29 Aug 2019 23:32:39 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 29 Aug 2019 23:32:38 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 29 Aug 2019 23:32:38 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56])\n\tby maili.marvell.com (Postfix) with ESMTP id EC3913F703F;\n\tThu, 29 Aug 2019 23:32:34 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=eAbokfrPtazYTwUriGJQuy+sFzGrjfAv2ppkeaklWuw=;\n\tb=bSerM1C727tRVxgKwHELq0zJuKc9Rzx3S86/ljwh1bLoak3UdRoyu4GtnaPYdPIZnIgy\n\tcyC7M0oTZN4oGFxUEc9OQlXboTiZ0GSr0ePW0LAMNI7v10MgG02Wo0qDNt/KuQ+xAhmR\n\t19LV6ShUWajbrN5aO+XHBEwQahsSDTmrDe4GKEt8NRBIpVCWZULpQ7BCx6Ih82jb9Baa\n\tFHm7r2lRcxy5sVReUG5HOxJX4pQHBtZeR+Az5fNfm1vcncAa8MzOeMya2d1LNIQd3p2J\n\t2dzZP2lk3najNn2zg2mrN96513DzUU/RUBEGS7VjeaB+7BwlAhlQqLuGVDw9LqoQgTGe\n\tzw== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Ankur Dwivedi <adwivedi@marvell.com>, Jerin Jacob <jerinj@marvell.com>, \n\tNarayana Prasad <pathreya@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n\tTejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Fri, 30 Aug 2019 11:58:19 +0530", "Message-ID": "<1567146501-8224-10-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "References": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.70,1.0.8\n\tdefinitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0", "Subject": "[dpdk-dev] [PATCH 09/11] crypto/octeontx2: add dequeue burst", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ankur Dwivedi <adwivedi@marvell.com>\n\nThis patch adds the dequeue burst callbacks for the OCTEON TX2\ncrypto driver. The completion code is checked during the dequeue\nand the respective status is set in the crypto operation.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/common/cpt/cpt_hw_types.h | 14 +++\n drivers/crypto/octeontx2/Makefile | 1 +\n drivers/crypto/octeontx2/meson.build | 1 +\n .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 16 +++\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 128 +++++++++++++++++++++\n 5 files changed, 160 insertions(+)", "diff": "diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h\nindex 4286512..e2b127d 100644\n--- a/drivers/common/cpt/cpt_hw_types.h\n+++ b/drivers/common/cpt/cpt_hw_types.h\n@@ -281,6 +281,20 @@ typedef union cpt_res_s {\n \t\tuint64_t reserved_64_127 : 64;\n #endif /* Word 1 - End */\n \t} s8x;\n+\tstruct cpt_res_s_9s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_17_63:47;\n+\t\tuint64_t doneint:1;\n+\t\tuint64_t uc_compcode:8;\n+\t\tuint64_t compcode:8;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t compcode:8;\n+\t\tuint64_t uc_compcode:8;\n+\t\tuint64_t doneint:1;\n+\t\tuint64_t reserved_17_63:47;\n+#endif /* Word 0 - End */\n+\t\tuint64_t reserved_64_127;\n+\t} s9x;\n } cpt_res_s_t;\n \n /**\ndiff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile\nindex 968efac..ce116b8 100644\n--- a/drivers/crypto/octeontx2/Makefile\n+++ b/drivers/crypto/octeontx2/Makefile\n@@ -24,6 +24,7 @@ CFLAGS += -O3\n CFLAGS += -I$(RTE_SDK)/drivers/common/cpt\n CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n \n ifneq ($(CONFIG_RTE_ARCH_64),y)\n CFLAGS += -Wno-int-to-pointer-cast\ndiff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build\nindex ee2e907..b6e5b73 100644\n--- a/drivers/crypto/octeontx2/meson.build\n+++ b/drivers/crypto/octeontx2/meson.build\n@@ -10,6 +10,7 @@ deps += ['common_cpt']\n deps += ['common_octeontx2']\n name = 'octeontx2_crypto'\n \n+allow_experimental_apis = true\n sources = files('otx2_cryptodev.c',\n \t\t'otx2_cryptodev_capabilities.c',\n \t\t'otx2_cryptodev_hw_access.c',\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\nindex 82718df..d787d74 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n@@ -12,6 +12,7 @@\n \n #include \"cpt_common.h\"\n #include \"cpt_hw_types.h\"\n+#include \"cpt_mcode_defines.h\"\n \n #include \"otx2_dev.h\"\n \n@@ -173,6 +174,21 @@ union otx2_cpt_lf_q_grp_ptr {\n \t} s;\n };\n \n+/*\n+ * Enumeration cpt_9x_comp_e\n+ *\n+ * CPT 9X Completion Enumeration\n+ * Enumerates the values of CPT_RES_S[COMPCODE].\n+ */\n+enum cpt_9x_comp_e {\n+\tCPT_9X_COMP_E_NOTDONE = 0x00,\n+\tCPT_9X_COMP_E_GOOD = 0x01,\n+\tCPT_9X_COMP_E_FAULT = 0x02,\n+\tCPT_9X_COMP_E_HWERR = 0x04,\n+\tCPT_9X_COMP_E_INSTERR = 0x05,\n+\tCPT_9X_COMP_E_LAST_ENTRY = 0x06\n+};\n+\n struct otx2_cpt_qp {\n \tuint32_t id;\n \t/**< Queue pair id */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex 74e6f1c..b21714c 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -486,6 +486,133 @@ otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \treturn count;\n }\n \n+static inline void\n+otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,\n+\t\t\t uintptr_t *rsp, uint8_t cc)\n+{\n+\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n+\t\tif (likely(cc == NO_ERR)) {\n+\t\t\t/* Verify authentication data if required */\n+\t\t\tif (unlikely(rsp[2]))\n+\t\t\t\tcompl_auth_verify(cop, (uint8_t *)rsp[2],\n+\t\t\t\t\t\t rsp[3]);\n+\t\t\telse\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\t} else {\n+\t\t\tif (cc == ERR_GC_ICV_MISCOMPARE)\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t\t\telse\n+\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t}\n+\n+\t\tif (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {\n+\t\t\tsym_session_clear(otx2_cryptodev_driver_id,\n+\t\t\t\t\t cop->sym->session);\n+\t\t\trte_mempool_put(qp->sess_mp, cop->sym->session);\n+\t\t\tcop->sym->session = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static __rte_always_inline uint8_t\n+otx2_cpt_compcode_get(struct cpt_request_info *req)\n+{\n+\tvolatile struct cpt_res_s_9s *res;\n+\tuint8_t ret;\n+\n+\tres = (volatile struct cpt_res_s_9s *)req->completion_addr;\n+\n+\tif (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {\n+\t\tif (rte_get_timer_cycles() < req->time_out)\n+\t\t\treturn ERR_REQ_PENDING;\n+\n+\t\tCPT_LOG_DP_ERR(\"Request timed out\");\n+\t\treturn ERR_REQ_TIMEOUT;\n+\t}\n+\n+\tif (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {\n+\t\tret = NO_ERR;\n+\t\tif (unlikely(res->uc_compcode)) {\n+\t\t\tret = res->uc_compcode;\n+\t\t\tCPT_LOG_DP_DEBUG(\"Request failed with microcode error\");\n+\t\t\tCPT_LOG_DP_DEBUG(\"MC completion code 0x%x\",\n+\t\t\t\t\t res->uc_compcode);\n+\t\t}\n+\t} else {\n+\t\tCPT_LOG_DP_DEBUG(\"HW completion code 0x%x\", res->compcode);\n+\n+\t\tret = res->compcode;\n+\t\tswitch (res->compcode) {\n+\t\tcase CPT_9X_COMP_E_INSTERR:\n+\t\t\tCPT_LOG_DP_ERR(\"Request failed with instruction error\");\n+\t\t\tbreak;\n+\t\tcase CPT_9X_COMP_E_FAULT:\n+\t\t\tCPT_LOG_DP_ERR(\"Request failed with DMA fault\");\n+\t\t\tbreak;\n+\t\tcase CPT_9X_COMP_E_HWERR:\n+\t\t\tCPT_LOG_DP_ERR(\"Request failed with hardware error\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tCPT_LOG_DP_ERR(\"Request failed with unknown completion code\");\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static uint16_t\n+otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tint i, nb_pending, nb_completed;\n+\tstruct otx2_cpt_qp *qp = qptr;\n+\tstruct pending_queue *pend_q;\n+\tstruct cpt_request_info *req;\n+\tstruct rte_crypto_op *cop;\n+\tuint8_t cc[nb_ops];\n+\tstruct rid *rid;\n+\tuintptr_t *rsp;\n+\tvoid *metabuf;\n+\n+\tpend_q = &qp->pend_q;\n+\n+\tnb_pending = pend_q->pending_count;\n+\n+\tif (nb_ops > nb_pending)\n+\t\tnb_ops = nb_pending;\n+\n+\tfor (i = 0; i < nb_ops; i++) {\n+\t\trid = &pend_q->rid_queue[pend_q->deq_head];\n+\t\treq = (struct cpt_request_info *)(rid->rid);\n+\n+\t\tcc[i] = otx2_cpt_compcode_get(req);\n+\n+\t\tif (unlikely(cc[i] == ERR_REQ_PENDING))\n+\t\t\tbreak;\n+\n+\t\tops[i] = req->op;\n+\n+\t\tMOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);\n+\t\tpend_q->pending_count -= 1;\n+\t}\n+\n+\tnb_completed = i;\n+\n+\tfor (i = 0; i < nb_completed; i++) {\n+\t\trsp = (void *)ops[i];\n+\n+\t\tmetabuf = (void *)rsp[0];\n+\t\tcop = (void *)rsp[1];\n+\n+\t\tops[i] = cop;\n+\n+\t\totx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);\n+\n+\t\tfree_op_meta(metabuf, qp->meta_info.pool);\n+\t}\n+\n+\treturn nb_completed;\n+}\n+\n /* PMD ops */\n \n static int\n@@ -536,6 +663,7 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev,\n \t}\n \n \tdev->enqueue_burst = otx2_cpt_enqueue_burst;\n+\tdev->dequeue_burst = otx2_cpt_dequeue_burst;\n \n \trte_mb();\n \treturn 0;\n", "prefixes": [ "09/11" ] }