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GET /api/patches/58292/?format=api
{ "id": 58292, "url": "http://patches.dpdk.org/api/patches/58292/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1567146501-8224-6-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567146501-8224-6-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567146501-8224-6-git-send-email-anoobj@marvell.com", "date": "2019-08-30T06:28:15", "name": "[05/11] crypto/octeontx2: add hardware definitions", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "bd37f7562e48bea5e3a18da3334dc67c0abd2e4d", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1567146501-8224-6-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 6176, "url": "http://patches.dpdk.org/api/series/6176/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6176", "date": "2019-08-30T06:28:10", "name": "add OCTEON TX2 crypto PMD", "version": 1, "mbox": "http://patches.dpdk.org/series/6176/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/58292/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/58292/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5F18F1E88E;\n\tFri, 30 Aug 2019 08:32:22 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id D6E3C1E886\n\tfor <dev@dpdk.org>; Fri, 30 Aug 2019 08:32:20 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx7U6UNd8027737; Thu, 29 Aug 2019 23:32:20 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg34-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 29 Aug 2019 23:32:20 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 29 Aug 2019 23:32:18 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 29 Aug 2019 23:32:18 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56])\n\tby maili.marvell.com (Postfix) with ESMTP id 250BD3F703F;\n\tThu, 29 Aug 2019 23:32:14 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=k1C0SmvVjMaqs0z5/3r1I0g3wVKR/tsLcqckgyJYvj4=;\n\tb=OTKVaGLs/PmvrOiKW/tUhf9mQHZZa8bQ8Gib7ZmbuhVOaBAP7bIcD+MPoRF02Z7K+NWf\n\t3eFh9XeOGyZgJIznxh1FwBSImWbJEkTf+aS0BK9ZCykv7L2Vq4QV23g0oDUS4OSaorG6\n\t68f1vN4Bo9m/AJXZ0JieNhlPwn1uUJp3E5swrqQ9XxZUabXDbmFHwl6V1960vOQBZNDs\n\t+7IV3jVDBjQaHZzuGYnAvsi+/y9Dhc+fmJmvRG1n5Y6PPNYjtGcCXmZQYMXyVg9us76T\n\tOyxHWyYUF95t8dQ0glFog6+I7Iu9ZFsPSsZTo9/OnreIMbVQ6jRq8ki7F6juNB+3qowk\n\tWA== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Ankur Dwivedi <adwivedi@marvell.com>, Jerin Jacob <jerinj@marvell.com>, \n\tNarayana Prasad <pathreya@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n\tTejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Fri, 30 Aug 2019 11:58:15 +0530", "Message-ID": "<1567146501-8224-6-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "References": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.70,1.0.8\n\tdefinitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0", "Subject": "[dpdk-dev] [PATCH 05/11] crypto/octeontx2: add hardware definitions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ankur Dwivedi <adwivedi@marvell.com>\n\nThis patch adds the hardware definitions for OCTEON TX2 crypto hardware.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 117 +++++++++++++++++++++\n 1 file changed, 117 insertions(+)", "diff": "diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\nindex 2af674d..441494e 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n@@ -11,15 +11,132 @@\n \n /* Register offsets */\n \n+/* LMT LF registers */\n+#define OTX2_LMT_LF_LMTLINE(a)\t\t(0x0ull | (uint64_t)(a) << 3)\n+\n /* CPT LF registers */\n+#define OTX2_CPT_LF_CTL\t\t\t0x10ull\n+#define OTX2_CPT_LF_INPROG\t\t0x40ull\n #define OTX2_CPT_LF_MISC_INT\t\t0xb0ull\n #define OTX2_CPT_LF_MISC_INT_ENA_W1S\t0xd0ull\n #define OTX2_CPT_LF_MISC_INT_ENA_W1C\t0xe0ull\n+#define OTX2_CPT_LF_Q_BASE\t\t0xf0ull\n+#define OTX2_CPT_LF_Q_SIZE\t\t0x100ull\n+#define OTX2_CPT_LF_NQ(a)\t\t(0x400ull | (uint64_t)(a) << 3)\n+\n+#define OTX2_CPT_AF_LF_CTL(a)\t\t(0x27000ull | (uint64_t)(a) << 3)\n \n #define OTX2_CPT_LF_BAR2(vf, q_id) \\\n \t\t((vf)->otx2_dev.bar2 + \\\n \t\t ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))\n \n+union otx2_cpt_lf_ctl {\n+\tuint64_t u;\n+\tstruct {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_8_63 : 56;\n+\t\tuint64_t fc_hyst_bits : 4;\n+\t\tuint64_t reserved_3_3 : 1;\n+\t\tuint64_t fc_up_crossing : 1;\n+\t\tuint64_t fc_ena : 1;\n+\t\tuint64_t ena : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t ena : 1;\n+\t\tuint64_t fc_ena : 1;\n+\t\tuint64_t fc_up_crossing : 1;\n+\t\tuint64_t reserved_3_3 : 1;\n+\t\tuint64_t fc_hyst_bits : 4;\n+\t\tuint64_t reserved_8_63 : 56;\n+#endif\n+\t} s;\n+};\n+\n+union otx2_cpt_lf_inprog {\n+\tuint64_t u;\n+\tstruct {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_48_63 : 16;\n+\t\tuint64_t gwb_cnt : 8;\n+\t\tuint64_t grb_cnt : 8;\n+\t\tuint64_t grb_partial : 1;\n+\t\tuint64_t reserved_18_30 : 13;\n+\t\tuint64_t grp_drp : 1;\n+\t\tuint64_t eena : 1;\n+\t\tuint64_t reserved_9_15 : 7;\n+\t\tuint64_t inflight : 9;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t inflight : 9;\n+\t\tuint64_t reserved_9_15 : 7;\n+\t\tuint64_t eena : 1;\n+\t\tuint64_t grp_drp : 1;\n+\t\tuint64_t reserved_18_30 : 13;\n+\t\tuint64_t grb_partial : 1;\n+\t\tuint64_t grb_cnt : 8;\n+\t\tuint64_t gwb_cnt : 8;\n+\t\tuint64_t reserved_48_63 : 16;\n+#endif\n+\t} s;\n+};\n+\n+union otx2_cpt_lf_q_base {\n+\tuint64_t u;\n+\tstruct {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_53_63 : 11;\n+\t\tuint64_t addr : 46;\n+\t\tuint64_t reserved_2_6 : 5;\n+\t\tuint64_t stopped : 1;\n+\t\tuint64_t fault : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t fault : 1;\n+\t\tuint64_t stopped : 1;\n+\t\tuint64_t reserved_2_6 : 5;\n+\t\tuint64_t addr : 46;\n+\t\tuint64_t reserved_53_63 : 11;\n+#endif\n+\t} s;\n+};\n+\n+union otx2_cpt_lf_q_size {\n+\tuint64_t u;\n+\tstruct {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_15_63 : 49;\n+\t\tuint64_t size_div40 : 15;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t size_div40 : 15;\n+\t\tuint64_t reserved_15_63 : 49;\n+#endif\n+\t} s;\n+};\n+\n+union otx2_cpt_af_lf_ctl {\n+\tuint64_t u;\n+\tstruct {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_56_63 : 8;\n+\t\tuint64_t grp : 8;\n+\t\tuint64_t reserved_17_47 : 31;\n+\t\tuint64_t nixtx_en : 1;\n+\t\tuint64_t reserved_11_15 : 5;\n+\t\tuint64_t cont_err : 1;\n+\t\tuint64_t pf_func_inst : 1;\n+\t\tuint64_t reserved_1_8 : 8;\n+\t\tuint64_t pri : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t pri : 1;\n+\t\tuint64_t reserved_1_8 : 8;\n+\t\tuint64_t pf_func_inst : 1;\n+\t\tuint64_t cont_err : 1;\n+\t\tuint64_t reserved_11_15 : 5;\n+\t\tuint64_t nixtx_en : 1;\n+\t\tuint64_t reserved_17_47 : 31;\n+\t\tuint64_t grp : 8;\n+\t\tuint64_t reserved_56_63 : 8;\n+#endif\n+\t} s;\n+};\n+\n void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);\n \n int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);\n", "prefixes": [ "05/11" ] }