Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/57952/?format=api
{ "id": 57952, "url": "http://patches.dpdk.org/api/patches/57952/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-56-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-56-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-56-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:57", "name": "[55/63] net/ice/base: update to register definition file", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "79c815ca3f7c0f0a3527f65044a0e9e9f2892242", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-56-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "http://patches.dpdk.org/api/series/6119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "http://patches.dpdk.org/series/6119/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57952/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57952/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C7C441C224;\n\tMon, 26 Aug 2019 12:51:44 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby dpdk.org (Postfix) with ESMTP id 4A2D11C13B\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:50:06 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:50:06 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:50:04 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402587\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tBruce Allan <bruce.w.allan@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:57 +0800", "Message-Id": "<20190826105105.19121-56-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 55/63] net/ice/base: update to register\n\tdefinition file", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Added register definitions for GL_MDCK_TX_TDPU and GL_MDET_TX_TDPU.\n\nSigned-off-by: Bruce Allan <bruce.w.allan@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_hw_autogen.h | 34 ++++++++++++++++++++++++++++++++++\n 1 file changed, 34 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h\nindex 2b423baf8..6f227adb8 100644\n--- a/drivers/net/ice/base/ice_hw_autogen.h\n+++ b/drivers/net/ice/base/ice_hw_autogen.h\n@@ -5330,6 +5330,29 @@\n #define GL_MDCK_RX\t\t\t\t0x0029422C /* Reset Source: CORER */\n #define GL_MDCK_RX_DESC_ADDR_S\t\t\t0\n #define GL_MDCK_RX_DESC_ADDR_M\t\t\tBIT(0)\n+#define GL_MDCK_TX_TDPU\t\t\t\t0x00049348 /* Reset Source: CORER */\n+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_S\t0\n+#define GL_MDCK_TX_TDPU_TTL_ERR_ITR_DIS_M\tBIT(0)\n+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_S 1\n+#define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)\n+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_S\t2\n+#define GL_MDCK_TX_TDPU_PCIE_UR_ITR_DIS_M\tBIT(2)\n+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_S\t3\n+#define GL_MDCK_TX_TDPU_MAL_OFFSET_ITR_DIS_M\tBIT(3)\n+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_S\t4\n+#define GL_MDCK_TX_TDPU_MAL_CMD_ITR_DIS_M\tBIT(4)\n+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_S\t5\n+#define GL_MDCK_TX_TDPU_BIG_PKT_SIZE_ITR_DIS_M\tBIT(5)\n+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_S 6\n+#define GL_MDCK_TX_TDPU_L2_ACCEPT_FAIL_ITR_DIS_M BIT(6)\n+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_S\t7\n+#define GL_MDCK_TX_TDPU_NIC_DSI_ITR_DIS_M\tBIT(7)\n+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_S 8\n+#define GL_MDCK_TX_TDPU_MAL_IPSEC_CMD_ITR_DIS_M BIT(8)\n+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_S 9\n+#define GL_MDCK_TX_TDPU_DSCP_CHECK_FAIL_ITR_DIS_M BIT(9)\n+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_S\t10\n+#define GL_MDCK_TX_TDPU_NIC_IPSEC_ITR_DIS_M\tBIT(10)\n #define GL_MDET_RX\t\t\t\t0x00294C00 /* Reset Source: CORER */\n #define GL_MDET_RX_QNUM_S\t\t\t0\n #define GL_MDET_RX_QNUM_M\t\t\tMAKEMASK(0x7FFF, 0)\n@@ -5363,6 +5386,17 @@\n #define GL_MDET_TX_TCLAN_MAL_TYPE_M\t\tMAKEMASK(0x1F, 26)\n #define GL_MDET_TX_TCLAN_VALID_S\t\t31\n #define GL_MDET_TX_TCLAN_VALID_M\t\tBIT(31)\n+#define GL_MDET_TX_TDPU\t\t\t\t0x00049350 /* Reset Source: CORER */\n+#define GL_MDET_TX_TDPU_QNUM_S\t\t\t0\n+#define GL_MDET_TX_TDPU_QNUM_M\t\t\tMAKEMASK(0x7FFF, 0)\n+#define GL_MDET_TX_TDPU_VF_NUM_S\t\t15\n+#define GL_MDET_TX_TDPU_VF_NUM_M\t\tMAKEMASK(0xFF, 15)\n+#define GL_MDET_TX_TDPU_PF_NUM_S\t\t23\n+#define GL_MDET_TX_TDPU_PF_NUM_M\t\tMAKEMASK(0x7, 23)\n+#define GL_MDET_TX_TDPU_MAL_TYPE_S\t\t26\n+#define GL_MDET_TX_TDPU_MAL_TYPE_M\t\tMAKEMASK(0x1F, 26)\n+#define GL_MDET_TX_TDPU_VALID_S\t\t\t31\n+#define GL_MDET_TX_TDPU_VALID_M\t\t\tBIT(31)\n #define GLRLAN_MDET\t\t\t\t0x00294200 /* Reset Source: CORER */\n #define GLRLAN_MDET_PCKT_EXTRCT_ERR_S\t\t0\n #define GLRLAN_MDET_PCKT_EXTRCT_ERR_M\t\tBIT(0)\n", "prefixes": [ "55/63" ] }