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GET /api/patches/57933/?format=api
{ "id": 57933, "url": "http://patches.dpdk.org/api/patches/57933/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-33-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-33-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-33-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:34", "name": "[32/63] net/ice/base: add more opcode and macros", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fbc1082b8172c00ea14f496e04432192fc814bc3", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-33-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "http://patches.dpdk.org/api/series/6119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "http://patches.dpdk.org/series/6119/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57933/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57933/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 95B841C1AB;\n\tMon, 26 Aug 2019 12:50:32 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 0DF651BF9E\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:49:23 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:49:23 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:49:22 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402309\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:34 +0800", "Message-Id": "<20190826105105.19121-33-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 32/63] net/ice/base: add more opcode and macros", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add more opcode and macros according to hardware spec.\n\n1. Add opcode for the NVM Update EMPR command.\n2. Add opcode for NVM save factory settings\n3. Add opcode for NVM Write/Write Activate calls\n4. Add loopback reporting to get link response macros\n5. Add link event defines macros\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 28 +++++++++++++++++++++++-----\n 1 file changed, 23 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex cc42180ea..b9e3bd5fa 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1575,7 +1575,12 @@ struct ice_aqc_get_link_status_data {\n #define ICE_AQ_LINK_TX_ACTIVE\t\t0\n #define ICE_AQ_LINK_TX_DRAINED\t\t1\n #define ICE_AQ_LINK_TX_FLUSHED\t\t3\n-\tu8 reserved2;\n+\tu8 lb_status;\n+#define ICE_AQ_LINK_LB_PHY_LCL\t\tBIT(0)\n+#define ICE_AQ_LINK_LB_PHY_RMT\t\tBIT(1)\n+#define ICE_AQ_LINK_LB_MAC_LCL\t\tBIT(2)\n+#define ICE_AQ_LINK_LB_PHY_IDX_S\t3\n+#define ICE_AQ_LINK_LB_PHY_IDX_M\t(0x7 << ICE_AQ_LB_PHY_IDX_S)\n \t__le16 max_frame_size;\n \tu8 cfg;\n #define ICE_AQ_LINK_25G_KR_FEC_EN\tBIT(0)\n@@ -1631,6 +1636,8 @@ struct ice_aqc_set_event_mask {\n #define ICE_AQ_LINK_EVENT_AN_COMPLETED\t\tBIT(7)\n #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL\tBIT(8)\n #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED\tBIT(9)\n+#define ICE_AQ_LINK_EVENT_TOPO_CONFLICT\t\tBIT(10)\n+#define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT\tBIT(11)\n \tu8\treserved1[6];\n };\n \n@@ -1690,20 +1697,26 @@ struct ice_aqc_sff_eeprom {\n \n /* NVM Read command (indirect 0x0701)\n * NVM Erase commands (direct 0x0702)\n- * NVM Update commands (indirect 0x0703)\n+ * NVM Write commands (indirect 0x0703)\n+ * NVM Write Activate commands (direct 0x0707)\n+ * NVM Shadow RAM Dump commands (direct 0x0707)\n */\n struct ice_aqc_nvm {\n \t__le16 offset_low;\n \tu8 offset_high;\n \tu8 cmd_flags;\n #define ICE_AQC_NVM_LAST_CMD\t\tBIT(0)\n-#define ICE_AQC_NVM_PCIR_REQ\t\tBIT(0)\t/* Used by NVM Update reply */\n-#define ICE_AQC_NVM_PRESERVATION_S\t1\n+#define ICE_AQC_NVM_PCIR_REQ\t\tBIT(0)\t/* Used by NVM Write reply */\n+#define ICE_AQC_NVM_PRESERVATION_S\t1 /* Used by NVM Write Activate only */\n #define ICE_AQC_NVM_PRESERVATION_M\t(3 << ICE_AQC_NVM_PRESERVATION_S)\n #define ICE_AQC_NVM_NO_PRESERVATION\t(0 << ICE_AQC_NVM_PRESERVATION_S)\n #define ICE_AQC_NVM_PRESERVE_ALL\tBIT(1)\n #define ICE_AQC_NVM_FACTORY_DEFAULT\t(2 << ICE_AQC_NVM_PRESERVATION_S)\n #define ICE_AQC_NVM_PRESERVE_SELECTED\t(3 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_ACTIV_SEL_NVM\tBIT(3) /* Write Activate/SR Dump only */\n+#define ICE_AQC_NVM_ACTIV_SEL_OROM\tBIT(4)\n+#define ICE_AQC_NVM_ACTIV_SEL_NETLIST\tBIT(5)\n+#define ICE_AQC_NVM_ACTIV_SEL_MASK\tMAKEMASK(0x7, 3)\n #define ICE_AQC_NVM_FLASH_ONLY\t\tBIT(7)\n \t__le16 module_typeid;\n \t__le16 length;\n@@ -2292,6 +2305,7 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_set_mac_cfg set_mac_cfg;\n \t\tstruct ice_aqc_set_event_mask set_event_mask;\n \t\tstruct ice_aqc_get_link_status get_link_status;\n+\t\tstruct ice_aqc_event_lan_overflow lan_overflow;\n \t} params;\n };\n \n@@ -2465,10 +2479,14 @@ enum ice_adminq_opc {\n \t/* NVM commands */\n \tice_aqc_opc_nvm_read\t\t\t\t= 0x0701,\n \tice_aqc_opc_nvm_erase\t\t\t\t= 0x0702,\n-\tice_aqc_opc_nvm_update\t\t\t\t= 0x0703,\n+\tice_aqc_opc_nvm_write\t\t\t\t= 0x0703,\n \tice_aqc_opc_nvm_cfg_read\t\t\t= 0x0704,\n \tice_aqc_opc_nvm_cfg_write\t\t\t= 0x0705,\n \tice_aqc_opc_nvm_checksum\t\t\t= 0x0706,\n+\tice_aqc_opc_nvm_write_activate\t\t\t= 0x0707,\n+\tice_aqc_opc_nvm_sr_dump\t\t\t\t= 0x0707,\n+\tice_aqc_opc_nvm_save_factory_settings\t\t= 0x0708,\n+\tice_aqc_opc_nvm_update_empr\t\t\t= 0x0709,\n \n \t/* LLDP commands */\n \tice_aqc_opc_lldp_get_mib\t\t\t= 0x0A00,\n", "prefixes": [ "32/63" ] }