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GET /api/patches/57906/?format=api
{ "id": 57906, "url": "http://patches.dpdk.org/api/patches/57906/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-11-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-11-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-11-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:12", "name": "[10/63] net/ice/base: improve debug print message", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7d08e7e7b16a33fa16544d8488ab30c790327977", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-11-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "http://patches.dpdk.org/api/series/6119/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "http://patches.dpdk.org/series/6119/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57906/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57906/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9D80E1C02F;\n\tMon, 26 Aug 2019 12:48:51 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 037B71BFF1\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:48:43 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:48:43 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:48:42 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402109\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:12 +0800", "Message-Id": "<20190826105105.19121-11-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 10/63] net/ice/base: improve debug print message", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Improve debug print message.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 41 +++++++++++++++++++------------------\n drivers/net/ice/base/ice_controlq.c | 10 +++++----\n 2 files changed, 27 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex cd94995f4..ae7837149 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -1955,7 +1955,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\tcase ICE_AQC_CAPS_VALID_FUNCTIONS:\n \t\t\tcaps->valid_functions = number;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: valid functions = %d\\n\", prefix,\n+\t\t\t\t \"%s: valid_functions (bitmap) = %d\\n\", prefix,\n \t\t\t\t caps->valid_functions);\n \n \t\t\t/* store func count for resource management purposes */\n@@ -1966,17 +1966,17 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\tif (dev_p) {\n \t\t\t\tdev_p->num_vsi_allocd_to_host = number;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num VSI alloc to host = %d\\n\",\n+\t\t\t\t\t \"%s: num_vsi_allocd_to_host = %d\\n\",\n \t\t\t\t\t prefix,\n \t\t\t\t\t dev_p->num_vsi_allocd_to_host);\n \t\t\t} else if (func_p) {\n \t\t\t\tfunc_p->guar_num_vsi =\n \t\t\t\t\tice_get_num_per_func(hw, ICE_MAX_VSI);\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num guaranteed VSI (fw) = %d\\n\",\n+\t\t\t\t\t \"%s: guar_num_vsi (fw) = %d\\n\",\n \t\t\t\t\t prefix, number);\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num guaranteed VSI = %d\\n\",\n+\t\t\t\t\t \"%s: guar_num_vsi = %d\\n\",\n \t\t\t\t\t prefix, func_p->guar_num_vsi);\n \t\t\t}\n \t\t\tbreak;\n@@ -1985,51 +1985,51 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\tcaps->active_tc_bitmap = logical_id;\n \t\t\tcaps->maxtc = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: DCB = %d\\n\", prefix, caps->dcb);\n+\t\t\t\t \"%s: dcb = %d\\n\", prefix, caps->dcb);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: active TC bitmap = %d\\n\", prefix,\n+\t\t\t\t \"%s: active_tc_bitmap = %d\\n\", prefix,\n \t\t\t\t caps->active_tc_bitmap);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: TC max = %d\\n\", prefix, caps->maxtc);\n+\t\t\t\t \"%s: maxtc = %d\\n\", prefix, caps->maxtc);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_RSS:\n \t\t\tcaps->rss_table_size = number;\n \t\t\tcaps->rss_table_entry_width = logical_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: RSS table size = %d\\n\", prefix,\n+\t\t\t\t \"%s: rss_table_size = %d\\n\", prefix,\n \t\t\t\t caps->rss_table_size);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: RSS table width = %d\\n\", prefix,\n+\t\t\t\t \"%s: rss_table_entry_width = %d\\n\", prefix,\n \t\t\t\t caps->rss_table_entry_width);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_RXQS:\n \t\t\tcaps->num_rxq = number;\n \t\t\tcaps->rxq_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: num Rx queues = %d\\n\", prefix,\n+\t\t\t\t \"%s: num_rxq = %d\\n\", prefix,\n \t\t\t\t caps->num_rxq);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: Rx first queue ID = %d\\n\", prefix,\n+\t\t\t\t \"%s: rxq_first_id = %d\\n\", prefix,\n \t\t\t\t caps->rxq_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_TXQS:\n \t\t\tcaps->num_txq = number;\n \t\t\tcaps->txq_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: num Tx queues = %d\\n\", prefix,\n+\t\t\t\t \"%s: num_txq = %d\\n\", prefix,\n \t\t\t\t caps->num_txq);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: Tx first queue ID = %d\\n\", prefix,\n+\t\t\t\t \"%s: txq_first_id = %d\\n\", prefix,\n \t\t\t\t caps->txq_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_MSIX:\n \t\t\tcaps->num_msix_vectors = number;\n \t\t\tcaps->msix_vector_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: MSIX vector count = %d\\n\", prefix,\n+\t\t\t\t \"%s: num_msix_vectors = %d\\n\", prefix,\n \t\t\t\t caps->num_msix_vectors);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: MSIX first vector index = %d\\n\", prefix,\n+\t\t\t\t \"%s: msix_vector_first_id = %d\\n\", prefix,\n \t\t\t\t caps->msix_vector_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_FD:\n@@ -2039,7 +2039,8 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\tif (dev_p) {\n \t\t\t\tdev_p->num_flow_director_fltr = number;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num FD filters = %d\\n\", prefix,\n+\t\t\t\t\t \"%s: num_flow_director_fltr = %d\\n\",\n+\t\t\t\t\t prefix,\n \t\t\t\t\t dev_p->num_flow_director_fltr);\n \t\t\t}\n \t\t\tif (func_p) {\n@@ -2052,17 +2053,17 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\t\t GLQF_FD_SIZE_FD_BSIZE_S;\n \t\t\t\tfunc_p->fd_fltr_best_effort = val;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num guaranteed FD filters = %d\\n\",\n+\t\t\t\t\t \"%s: fd_fltr_guar = %d\\n\",\n \t\t\t\t\t prefix, func_p->fd_fltr_guar);\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num best effort FD filters = %d\\n\",\n+\t\t\t\t\t \"%s: fd_fltr_best_effort = %d\\n\",\n \t\t\t\t\t prefix, func_p->fd_fltr_best_effort);\n \t\t\t}\n \t\t\tbreak;\n \t\t}\n \t\tcase ICE_AQC_CAPS_MAX_MTU:\n \t\t\tcaps->max_mtu = number;\n-\t\t\tice_debug(hw, ICE_DBG_INIT, \"%s: max MTU = %d\\n\",\n+\t\t\tice_debug(hw, ICE_DBG_INIT, \"%s: max_mtu = %d\\n\",\n \t\t\t\t prefix, caps->max_mtu);\n \t\t\tbreak;\n \t\tdefault:\n@@ -2081,7 +2082,7 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t/* Max 4 TCs per port */\n \t\tcaps->maxtc = 4;\n \t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t \"%s: TC max = %d (based on #ports)\\n\", prefix,\n+\t\t\t \"%s: maxtc = %d (based on #ports)\\n\", prefix,\n \t\t\t caps->maxtc);\n \t}\n }\ndiff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c\nindex 80322e70d..8070bb9a7 100644\n--- a/drivers/net/ice/base/ice_controlq.c\n+++ b/drivers/net/ice/base/ice_controlq.c\n@@ -968,7 +968,7 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t}\n \n \t/* Debug desc and buffer */\n-\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\tice_debug(hw, ICE_DBG_AQ_DESC,\n \t\t \"ATQ: Control Send queue desc and buffer:\\n\");\n \n \tice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);\n@@ -1008,7 +1008,8 @@ ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t\tretval = LE16_TO_CPU(desc->retval);\n \t\tif (retval) {\n \t\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n-\t\t\t\t \"Control Send Queue command completed with error 0x%x\\n\",\n+\t\t\t\t \"Control Send Queue command 0x%04X completed with error 0x%X\\n\",\n+\t\t\t\t LE16_TO_CPU(desc->opcode),\n \t\t\t\t retval);\n \n \t\t\t/* strip off FW internal code */\n@@ -1113,7 +1114,8 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \tif (flags & ICE_AQ_FLAG_ERR) {\n \t\tret_code = ICE_ERR_AQ_ERROR;\n \t\tice_debug(hw, ICE_DBG_AQ_MSG,\n-\t\t\t \"Control Receive Queue Event received with error 0x%x\\n\",\n+\t\t\t \"Control Receive Queue Event 0x%04X received with error 0x%X\\n\",\n+\t\t\t LE16_TO_CPU(desc->opcode),\n \t\t\t cq->rq_last_status);\n \t}\n \tice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);\n@@ -1123,7 +1125,7 @@ ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t\tice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,\n \t\t\t e->msg_len, ICE_DMA_TO_NONDMA);\n \n-\tice_debug(hw, ICE_DBG_AQ_MSG, \"ARQ: desc and buffer:\\n\");\n+\tice_debug(hw, ICE_DBG_AQ_DESC, \"ARQ: desc and buffer:\\n\");\n \n \tice_debug_cq(hw, (void *)desc, e->msg_buf,\n \t\t cq->rq_buf_size);\n", "prefixes": [ "10/63" ] }