Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 57872,
    "url": "http://patches.dpdk.org/api/patches/57872/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190823144602.58213-8-jasvinder.singh@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190823144602.58213-8-jasvinder.singh@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190823144602.58213-8-jasvinder.singh@intel.com",
    "date": "2019-08-23T14:45:54",
    "name": "[07/15] sched: update memory compute to support flexiblity",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "7be787898c5d7759d82fbbc39b4bd85ddbf9e32e",
    "submitter": {
        "id": 285,
        "url": "http://patches.dpdk.org/api/people/285/?format=api",
        "name": "Jasvinder Singh",
        "email": "jasvinder.singh@intel.com"
    },
    "delegate": {
        "id": 10018,
        "url": "http://patches.dpdk.org/api/users/10018/?format=api",
        "username": "cristian_dumitrescu",
        "first_name": "Cristian",
        "last_name": "Dumitrescu",
        "email": "cristian.dumitrescu@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190823144602.58213-8-jasvinder.singh@intel.com/mbox/",
    "series": [
        {
            "id": 6115,
            "url": "http://patches.dpdk.org/api/series/6115/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6115",
            "date": "2019-08-23T14:45:47",
            "name": "sched: subport level configuration of pipe nodes",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/6115/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/57872/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/57872/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C678A1C06B;\n\tFri, 23 Aug 2019 16:46:26 +0200 (CEST)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 1EECD1BFB4\n\tfor <dev@dpdk.org>; Fri, 23 Aug 2019 16:46:12 +0200 (CEST)",
            "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t23 Aug 2019 07:46:12 -0700",
            "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby orsmga001.jf.intel.com with ESMTP; 23 Aug 2019 07:46:11 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.64,421,1559545200\"; d=\"scan'208\";a=\"263211281\"",
        "From": "Jasvinder Singh <jasvinder.singh@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "cristian.dumitrescu@intel.com,\n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>",
        "Date": "Fri, 23 Aug 2019 15:45:54 +0100",
        "Message-Id": "<20190823144602.58213-8-jasvinder.singh@intel.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190823144602.58213-1-jasvinder.singh@intel.com>",
        "References": "<20190823144602.58213-1-jasvinder.singh@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 07/15] sched: update memory compute to support\n\tflexiblity",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Update memory footprint compute function for allowing subports of\nthe same port to have different configuration in terms of number of\npipes, pipe queue sizes, etc.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 102 +++++++++++------------------------\n lib/librte_sched/rte_sched.h |   8 +--\n 2 files changed, 36 insertions(+), 74 deletions(-)",
    "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex a5e4c45b4..f8d13c66d 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -495,70 +495,6 @@ rte_sched_port_check_params(struct rte_sched_port_params *params)\n \treturn 0;\n }\n \n-static uint32_t\n-rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sched_port_array array)\n-{\n-\tuint32_t n_subports_per_port = params->n_subports_per_port;\n-\tuint32_t n_pipes_per_subport = params->n_pipes_per_subport;\n-\tuint32_t n_pipes_per_port = n_pipes_per_subport * n_subports_per_port;\n-\tuint32_t n_queues_per_port = RTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport * n_subports_per_port;\n-\n-\tuint32_t size_subport = n_subports_per_port * sizeof(struct rte_sched_subport);\n-\tuint32_t size_pipe = n_pipes_per_port * sizeof(struct rte_sched_pipe);\n-\tuint32_t size_queue = n_queues_per_port * sizeof(struct rte_sched_queue);\n-\tuint32_t size_queue_extra\n-\t\t= n_queues_per_port * sizeof(struct rte_sched_queue_extra);\n-\tuint32_t size_pipe_profiles\n-\t\t= params->n_max_pipe_profiles * sizeof(struct rte_sched_pipe_profile);\n-\tuint32_t size_bmp_array = rte_bitmap_get_memory_footprint(n_queues_per_port);\n-\tuint32_t size_per_pipe_queue_array, size_queue_array;\n-\n-\tuint32_t base, i;\n-\n-\tsize_per_pipe_queue_array = 0;\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tif (i < RTE_SCHED_TRAFFIC_CLASS_BE)\n-\t\t\tsize_per_pipe_queue_array +=\n-\t\t\t\tparams->qsize[i] * sizeof(struct rte_mbuf *);\n-\t\telse\n-\t\t\tsize_per_pipe_queue_array += RTE_SCHED_MAX_QUEUES_PER_TC *\n-\t\t\t\tparams->qsize[i] * sizeof(struct rte_mbuf *);\n-\t}\n-\tsize_queue_array = n_pipes_per_port * size_per_pipe_queue_array;\n-\n-\tbase = 0;\n-\n-\tif (array == e_RTE_SCHED_PORT_ARRAY_SUBPORT)\n-\t\treturn base;\n-\tbase += RTE_CACHE_LINE_ROUNDUP(size_subport);\n-\n-\tif (array == e_RTE_SCHED_PORT_ARRAY_PIPE)\n-\t\treturn base;\n-\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe);\n-\n-\tif (array == e_RTE_SCHED_PORT_ARRAY_QUEUE)\n-\t\treturn base;\n-\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue);\n-\n-\tif (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA)\n-\t\treturn base;\n-\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);\n-\n-\tif (array == e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES)\n-\t\treturn base;\n-\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);\n-\n-\tif (array == e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY)\n-\t\treturn base;\n-\tbase += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);\n-\n-\tif (array == e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY)\n-\t\treturn base;\n-\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_array);\n-\n-\treturn base;\n-}\n-\n static uint32_t\n rte_sched_subport_get_array_base(struct rte_sched_subport_params *params,\n \tuint32_t n_max_pipe_profiles,\n@@ -880,22 +816,46 @@ rte_sched_subport_check_params(struct rte_sched_subport_params *params,\n }\n \n uint32_t\n-rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n+rte_sched_port_get_memory_footprint(struct rte_sched_port_params *port_params,\n+\tstruct rte_sched_subport_params **subport_params)\n {\n-\tuint32_t size0, size1;\n+\tuint32_t size0 = 0, size1 = 0, i;\n \tint status;\n \n-\tstatus = rte_sched_port_check_params(params);\n+\tstatus = rte_sched_port_check_params(port_params);\n \tif (status != 0) {\n-\t\tRTE_LOG(NOTICE, SCHED,\n-\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Port scheduler port params check failed (%d)\\n\",\n+\t\t\t__func__, status);\n \n \t\treturn 0;\n \t}\n \n+\tfor (i = 0; i < port_params->n_subports_per_port; i++) {\n+\t\tstruct rte_sched_subport_params *sp = subport_params[i];\n+\n+\t\tstatus = rte_sched_subport_check_params(sp,\n+\t\t\t\tport_params->n_max_pipes_per_subport,\n+\t\t\t\tport_params->n_max_pipe_profiles,\n+\t\t\t\tport_params->rate);\n+\t\tif (status != 0) {\n+\t\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\t\"%s: Port scheduler subport params check failed (%d)\\n\",\n+\t\t\t\t__func__, status);\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n \tsize0 = sizeof(struct rte_sched_port);\n-\tsize1 = rte_sched_port_get_array_base(params,\n-\t\t\te_RTE_SCHED_PORT_ARRAY_TOTAL);\n+\n+\tfor (i = 0; i < port_params->n_subports_per_port; i++) {\n+\t\tstruct rte_sched_subport_params *sp = subport_params[i];\n+\n+\t\tsize1 += rte_sched_subport_get_array_base(sp,\n+\t\t\t\t\tport_params->n_max_pipe_profiles,\n+\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_TOTAL);\n+\t}\n \n \treturn size0 + size1;\n }\ndiff --git a/lib/librte_sched/rte_sched.h b/lib/librte_sched/rte_sched.h\nindex 56e9fbfa7..ea2b07448 100644\n--- a/lib/librte_sched/rte_sched.h\n+++ b/lib/librte_sched/rte_sched.h\n@@ -364,14 +364,16 @@ rte_sched_pipe_config(struct rte_sched_port *port,\n /**\n  * Hierarchical scheduler memory footprint size per port\n  *\n- * @param params\n+ * @param port_params\n  *   Port scheduler configuration parameter structure\n+ * @param subport_params\n+ *   Array of subport parameter structures\n  * @return\n  *   Memory footprint size in bytes upon success, 0 otherwise\n  */\n uint32_t\n-rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params);\n-\n+rte_sched_port_get_memory_footprint(struct rte_sched_port_params *port_params,\n+\tstruct rte_sched_subport_params **subport_params);\n /*\n  * Statistics\n  *\n",
    "prefixes": [
        "07/15"
    ]
}