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GET /api/patches/57869/?format=api
{ "id": 57869, "url": "http://patches.dpdk.org/api/patches/57869/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190823144602.58213-5-jasvinder.singh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190823144602.58213-5-jasvinder.singh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190823144602.58213-5-jasvinder.singh@intel.com", "date": "2019-08-23T14:45:51", "name": "[04/15] shced: add pipe config to subport level", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "af20bc147c8de4d6bba087aa36092a7c9e253d38", "submitter": { "id": 285, "url": "http://patches.dpdk.org/api/people/285/?format=api", "name": "Jasvinder Singh", "email": "jasvinder.singh@intel.com" }, "delegate": { "id": 10018, "url": "http://patches.dpdk.org/api/users/10018/?format=api", "username": "cristian_dumitrescu", "first_name": "Cristian", "last_name": "Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190823144602.58213-5-jasvinder.singh@intel.com/mbox/", "series": [ { "id": 6115, "url": "http://patches.dpdk.org/api/series/6115/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6115", "date": "2019-08-23T14:45:47", "name": "sched: subport level configuration of pipe nodes", "version": 1, "mbox": "http://patches.dpdk.org/series/6115/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57869/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57869/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B13361C00D;\n\tFri, 23 Aug 2019 16:46:19 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id B58651BF08\n\tfor <dev@dpdk.org>; Fri, 23 Aug 2019 16:46:08 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t23 Aug 2019 07:46:08 -0700", "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby orsmga001.jf.intel.com with ESMTP; 23 Aug 2019 07:46:06 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,421,1559545200\"; d=\"scan'208\";a=\"263211249\"", "From": "Jasvinder Singh <jasvinder.singh@intel.com>", "To": "dev@dpdk.org", "Cc": "cristian.dumitrescu@intel.com,\n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>", "Date": "Fri, 23 Aug 2019 15:45:51 +0100", "Message-Id": "<20190823144602.58213-5-jasvinder.singh@intel.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190823144602.58213-1-jasvinder.singh@intel.com>", "References": "<20190823144602.58213-1-jasvinder.singh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 04/15] shced: add pipe config to subport level", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add pipes configuration from the port level to allow different\nsubports of the same port to have different configuration in terms\nof number of pipes, pipe queue sizes, etc.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 390 ++++++++++++++++++++++++++++++-----\n 1 file changed, 334 insertions(+), 56 deletions(-)", "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex db8b0485a..1491cb695 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -559,24 +559,92 @@ rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sch\n \treturn base;\n }\n \n-uint32_t\n-rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n+static uint32_t\n+rte_sched_subport_get_array_base(struct rte_sched_subport_params *params,\n+\tuint32_t n_max_pipe_profiles,\n+\tenum rte_sched_subport_array array)\n {\n-\tuint32_t size0, size1;\n-\tint status;\n+\tuint32_t n_pipes_per_subport = params->n_pipes_per_subport;\n+\tuint32_t n_subport_pipe_queues =\n+\t\tRTE_SCHED_QUEUES_PER_PIPE * n_pipes_per_subport;\n \n-\tstatus = rte_sched_port_check_params(params);\n-\tif (status != 0) {\n-\t\tRTE_LOG(NOTICE, SCHED,\n-\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\tuint32_t size_pipe = n_pipes_per_subport * sizeof(struct rte_sched_pipe);\n+\tuint32_t size_queue =\n+\t\tn_subport_pipe_queues * sizeof(struct rte_sched_queue);\n+\tuint32_t size_queue_extra\n+\t\t= n_subport_pipe_queues * sizeof(struct rte_sched_queue_extra);\n+\tuint32_t size_pipe_profiles = n_max_pipe_profiles *\n+\t\tsizeof(struct rte_sched_pipe_profile);\n+\tuint32_t size_bmp_array =\n+\t\trte_bitmap_get_memory_footprint(n_subport_pipe_queues);\n+\tuint32_t size_per_pipe_queue_array, size_queue_array;\n \n-\t\treturn 0;\n+\tuint32_t base, i;\n+\n+\tsize_per_pipe_queue_array = 0;\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\tif (i < RTE_SCHED_TRAFFIC_CLASS_BE)\n+\t\t\tsize_per_pipe_queue_array +=\n+\t\t\t\tparams->qsize[i] * sizeof(struct rte_mbuf *);\n+\t\telse\n+\t\t\tsize_per_pipe_queue_array += RTE_SCHED_MAX_QUEUES_PER_TC *\n+\t\t\t\tparams->qsize[i] * sizeof(struct rte_mbuf *);\n \t}\n+\tsize_queue_array = n_pipes_per_subport * size_per_pipe_queue_array;\n \n-\tsize0 = sizeof(struct rte_sched_port);\n-\tsize1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);\n+\tbase = 0;\n \n-\treturn size0 + size1;\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_PIPE)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE_EXTRA)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_PIPE_PROFILES)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_BMP_ARRAY)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_array);\n+\n+\treturn base;\n+}\n+\n+static void\n+rte_sched_subport_config_qsize(struct rte_sched_subport *subport)\n+{\n+\tuint32_t i;\n+\n+\tsubport->qsize_add[0] = 0;\n+\n+\t/* Strict prority traffic class */\n+\tfor (i = 1; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n+\t\tsubport->qsize_add[i] = subport->qsize_add[i-1] + subport->qsize[i-1];\n+\n+\t/* Best-effort traffic class */\n+\tsubport->qsize_add[RTE_SCHED_TRAFFIC_CLASS_BE + 1] =\n+\t\tsubport->qsize_add[RTE_SCHED_TRAFFIC_CLASS_BE] +\n+\t\tsubport->qsize[RTE_SCHED_TRAFFIC_CLASS_BE];\n+\tsubport->qsize_add[RTE_SCHED_TRAFFIC_CLASS_BE + 2] =\n+\t\tsubport->qsize_add[RTE_SCHED_TRAFFIC_CLASS_BE + 1] +\n+\t\tsubport->qsize[RTE_SCHED_TRAFFIC_CLASS_BE];\n+\tsubport->qsize_add[RTE_SCHED_TRAFFIC_CLASS_BE + 3] =\n+\t\tsubport->qsize_add[RTE_SCHED_TRAFFIC_CLASS_BE + 2] +\n+\t\tsubport->qsize[RTE_SCHED_TRAFFIC_CLASS_BE];\n+\n+\tsubport->qsize_sum = subport->qsize_add[RTE_SCHED_TRAFFIC_CLASS_BE + 3] +\n+\t\tsubport->qsize[RTE_SCHED_TRAFFIC_CLASS_BE];\n }\n \n static void\n@@ -688,6 +756,126 @@ rte_sched_pipe_profile_convert(struct rte_sched_port *port,\n \tdst->wrr_cost[3] = (uint8_t) wrr_cost[3];\n }\n \n+static int\n+rte_sched_subport_check_params(struct rte_sched_subport_params *params,\n+\tuint32_t n_max_pipes_per_subport,\n+\tuint32_t n_max_pipe_profiles,\n+\tuint32_t rate)\n+{\n+\tuint32_t i;\n+\n+\t/* Check user parameters */\n+\tif (params == NULL) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for parameter params\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tb_rate == 0 || params->tb_rate > rate) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for tb rate\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tb_size == 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for tb size\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* qsize: if non-zero, power of 2,\n+\t * no bigger than 32K (due to 16-bit read/write pointers)\n+\t */\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\tuint16_t qsize = params->qsize[i];\n+\n+\t\tif (qsize != 0 && !rte_is_power_of_2(qsize)) {\n+\t\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\t\"%s: Incorrect value for qsize\\n\", __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\tuint32_t tc_rate = params->tc_rate[i];\n+\t\tuint16_t qsize = params->qsize[i];\n+\n+\t\tif ((qsize == 0 && tc_rate != 0) ||\n+\t\t\t(qsize != 0 && tc_rate == 0) ||\n+\t\t\t(tc_rate > params->tb_rate)) {\n+\t\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\t\"%s: Incorrect value for tc rate\\n\", __func__);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tif (params->qsize[RTE_SCHED_TRAFFIC_CLASS_BE] == 0 ||\n+\t\tparams->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE] == 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect qsize or tc rate(best effort)\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (params->tc_period == 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for tc period\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* n_pipes_per_subport: non-zero, power of 2 */\n+\tif (params->n_pipes_per_subport == 0 ||\n+\t\tparams->n_pipes_per_subport > n_max_pipes_per_subport ||\n+\t !rte_is_power_of_2(params->n_pipes_per_subport)) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for pipes number\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* pipe_profiles and n_pipe_profiles */\n+\tif (params->pipe_profiles == NULL ||\n+\t params->n_pipe_profiles == 0 ||\n+\t\tparams->n_pipe_profiles > n_max_pipe_profiles) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for pipe profiles\\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < params->n_pipe_profiles; i++) {\n+\t\tstruct rte_sched_pipe_params *p = params->pipe_profiles + i;\n+\t\tint status;\n+\n+\t\tstatus = pipe_profile_check(p, rate, ¶ms->qsize[0]);\n+\t\tif (status != 0) {\n+\t\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\t\"%s: Pipe profile check failed(%d)\\n\", __func__, status);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+uint32_t\n+rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n+{\n+\tuint32_t size0, size1;\n+\tint status;\n+\n+\tstatus = rte_sched_port_check_params(params);\n+\tif (status != 0) {\n+\t\tRTE_LOG(NOTICE, SCHED,\n+\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tsize0 = sizeof(struct rte_sched_port);\n+\tsize1 = rte_sched_port_get_array_base(params,\n+\t\t\te_RTE_SCHED_PORT_ARRAY_TOTAL);\n+\n+\treturn size0 + size1;\n+}\n+\n struct rte_sched_port *\n rte_sched_port_config(struct rte_sched_port_params *params)\n {\n@@ -809,7 +997,7 @@ rte_sched_port_free(struct rte_sched_port *port)\n static void\n rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)\n {\n-\tstruct rte_sched_subport *s = port->subport + i;\n+\tstruct rte_sched_subport *s = port->subports[i];\n \n \tRTE_LOG(DEBUG, SCHED, \"Low level config for subport %u:\\n\"\n \t\t\"\tToken bucket: period = %u, credits per period = %u, size = %u\\n\"\n@@ -844,72 +1032,80 @@ rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)\n \t\ts->tc_ov_wm_max);\n }\n \n+static void\n+rte_sched_free_memory(struct rte_sched_port *port, uint32_t n_subports)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < n_subports; i++) {\n+\t\tstruct rte_sched_subport *subport = port->subports[i];\n+\n+\t\trte_sched_subport_free(port, subport);\n+\t}\n+\n+\trte_free(port);\n+}\n+\n int\n rte_sched_subport_config(struct rte_sched_port *port,\n \tuint32_t subport_id,\n \tstruct rte_sched_subport_params *params)\n {\n-\tstruct rte_sched_subport *s;\n-\tuint32_t i;\n+\tstruct rte_sched_subport *s = NULL;\n+\tuint32_t n_subports = subport_id;\n+\tuint32_t n_subport_pipe_queues, i;\n+\tuint32_t size0, size1, bmp_mem_size;\n+\tint status;\n \n \t/* Check user parameters */\n \tif (port == NULL) {\n \t\tRTE_LOG(ERR, SCHED,\n \t\t\t\"%s: Incorrect value for parameter port\\n\", __func__);\n-\t\treturn -EINVAL;\n+\t\treturn 0;\n \t}\n \n \tif (subport_id >= port->n_subports_per_port) {\n \t\tRTE_LOG(ERR, SCHED,\n \t\t\t\"%s: Incorrect value for subport id\\n\", __func__);\n-\t\treturn -EINVAL;\n-\t}\n \n-\tif (params == NULL) {\n-\t\tRTE_LOG(ERR, SCHED,\n-\t\t\t\"%s: Incorrect value for parameter params\\n\", __func__);\n+\t\trte_sched_free_memory(port, n_subports);\n \t\treturn -EINVAL;\n \t}\n \n-\tif (params->tb_rate == 0 || params->tb_rate > port->rate) {\n-\t\tRTE_LOG(ERR, SCHED,\n-\t\t\t\"%s: Incorrect value for tb rate\\n\", __func__);\n-\t\treturn -EINVAL;\n-\t}\n+\tstatus = rte_sched_subport_check_params(params,\n+\t\tport->n_max_pipes_per_subport,\n+\t\tport->n_max_pipe_profiles,\n+\t\tport->rate);\n+\tif (status != 0) {\n+\t\tRTE_LOG(NOTICE, SCHED,\n+\t\t\t\"%s: Port scheduler params check failed (%d)\\n\",\n+\t\t\t__func__, status);\n \n-\tif (params->tb_size == 0) {\n-\t\tRTE_LOG(ERR, SCHED,\n-\t\t\t\"%s: Incorrect value for tb size\\n\", __func__);\n+\t\trte_sched_free_memory(port, n_subports);\n \t\treturn -EINVAL;\n \t}\n \n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tuint32_t tc_rate = params->tc_rate[i];\n-\t\tuint16_t qsize = port->qsize[i];\n+\t/* Determine the amount of memory to allocate */\n+\tsize0 = sizeof(struct rte_sched_subport);\n+\tsize1 = rte_sched_subport_get_array_base(params,\n+\t\t\tport->n_max_pipe_profiles,\n+\t\t\te_RTE_SCHED_SUBPORT_ARRAY_TOTAL);\n \n-\t\tif ((qsize == 0 && tc_rate != 0) ||\n-\t\t\t(qsize != 0 && tc_rate == 0) ||\n-\t\t\t(tc_rate > params->tb_rate)) {\n-\t\t\tRTE_LOG(ERR, SCHED,\n-\t\t\t\t\"%s: Incorrect value for tc rate\\n\", __func__);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\tif (port->qsize[RTE_SCHED_TRAFFIC_CLASS_BE] == 0 ||\n-\t\tparams->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE] == 0) {\n+\t/* Allocate memory to store the data structures */\n+\ts = rte_zmalloc_socket(\"subport_params\", size0 + size1,\n+\t\tRTE_CACHE_LINE_SIZE, port->socket);\n+\tif (s == NULL) {\n \t\tRTE_LOG(ERR, SCHED,\n-\t\t\t\"%s: Incorrect value for tc rate(best effort)\\n\", __func__);\n-\t\treturn -EINVAL;\n-\t}\n+\t\t\t\"%s: Memory allocation fails\\n\", __func__);\n \n-\tif (params->tc_period == 0) {\n-\t\tRTE_LOG(ERR, SCHED,\n-\t\t\t\"%s: Incorrect value for tc period\\n\", __func__);\n-\t\treturn -EINVAL;\n+\t\trte_sched_free_memory(port, n_subports);\n+\t\treturn -ENOMEM;\n \t}\n \n-\ts = port->subport + subport_id;\n+\tn_subports++;\n+\n+\t/* Port */\n+\tport->subports[subport_id] = s;\n \n \t/* Token Bucket (TB) */\n \tif (params->tb_rate == port->rate) {\n@@ -929,26 +1125,108 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t/* Traffic Classes (TCs) */\n \ts->tc_period = rte_sched_time_ms_to_bytes(params->tc_period, port->rate);\n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tif (port->qsize[i])\n+\t\tif (params->qsize[i])\n \t\t\ts->tc_credits_per_period[i]\n \t\t\t\t= rte_sched_time_ms_to_bytes(params->tc_period,\n-\t\t\t\t\t\t\t\t params->tc_rate[i]);\n-\n+\t\t\t\t\tparams->tc_rate[i]);\n \t}\n \ts->tc_time = port->time + s->tc_period;\n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tif (port->qsize[i])\n+\t\tif (params->qsize[i])\n \t\t\ts->tc_credits[i] = s->tc_credits_per_period[i];\n \n+\t/* compile time checks */\n+\tRTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS == 0);\n+\tRTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS &\n+\t\t(RTE_SCHED_PORT_N_GRINDERS - 1));\n+\n+\t/* User parameters */\n+\ts->n_pipes_per_subport = params->n_pipes_per_subport;\n+\tmemcpy(s->qsize, params->qsize, sizeof(params->qsize));\n+\ts->n_pipe_profiles = params->n_pipe_profiles;\n+\n+#ifdef RTE_SCHED_RED\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\tuint32_t j;\n+\n+\t\tfor (j = 0; j < RTE_COLORS; j++) {\n+\t\t\t/* if min/max are both zero, then RED is disabled */\n+\t\t\tif ((params->red_params[i][j].min_th |\n+\t\t\t params->red_params[i][j].max_th) == 0) {\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tif (rte_red_config_init(&s->red_config[i][j],\n+\t\t\t\tparams->red_params[i][j].wq_log2,\n+\t\t\t\tparams->red_params[i][j].min_th,\n+\t\t\t\tparams->red_params[i][j].max_th,\n+\t\t\t\tparams->red_params[i][j].maxp_inv) != 0) {\n+\t\t\t\trte_sched_free_memory(port, n_subports);\n+\n+\t\t\t\tRTE_LOG(NOTICE, SCHED,\n+\t\t\t\t\"%s: RED configuration init fails\\n\", __func__);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t}\n+\t}\n+#endif\n+\n+\t/* Scheduling loop detection */\n+\ts->pipe_loop = RTE_SCHED_PIPE_INVALID;\n+\ts->pipe_exhaustion = 0;\n+\n+\t/* Grinders */\n+\ts->busy_grinders = 0;\n+\n+\t/* Queue base calculation */\n+\trte_sched_subport_config_qsize(s);\n+\n+\t/* Large data structures */\n+\ts->pipe = (struct rte_sched_pipe *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\tport->n_max_pipe_profiles, e_RTE_SCHED_SUBPORT_ARRAY_PIPE));\n+\ts->queue = (struct rte_sched_queue *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\tport->n_max_pipe_profiles, e_RTE_SCHED_SUBPORT_ARRAY_QUEUE));\n+\ts->queue_extra = (struct rte_sched_queue_extra *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\tport->n_max_pipe_profiles, e_RTE_SCHED_SUBPORT_ARRAY_QUEUE_EXTRA));\n+\ts->pipe_profiles = (struct rte_sched_pipe_profile *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\tport->n_max_pipe_profiles, e_RTE_SCHED_SUBPORT_ARRAY_PIPE_PROFILES));\n+\ts->bmp_array = s->memory + rte_sched_subport_get_array_base(params,\n+\t\tport->n_max_pipe_profiles, e_RTE_SCHED_SUBPORT_ARRAY_BMP_ARRAY);\n+\ts->queue_array = (struct rte_mbuf **)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\tport->n_max_pipe_profiles, e_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY));\n+\n+\t/* Bitmap */\n+\tn_subport_pipe_queues = rte_sched_subport_pipe_queues(s);\n+\tbmp_mem_size = rte_bitmap_get_memory_footprint(n_subport_pipe_queues);\n+\ts->bmp = rte_bitmap_init(n_subport_pipe_queues, s->bmp_array,\n+\t\t\t\tbmp_mem_size);\n+\tif (s->bmp == NULL) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Subport bitmap init error\\n\", __func__);\n+\n+\t\trte_sched_free_memory(port, n_subports);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++)\n+\t\ts->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;\n+\n+#ifdef RTE_SCHED_SUBPORT_TC_OV\n \t/* TC oversubscription */\n \ts->tc_ov_wm_min = port->mtu;\n \ts->tc_ov_wm_max = rte_sched_time_ms_to_bytes(params->tc_period,\n-\t\t\t\t\t\t port->pipe_tc_be_rate_max);\n+\t\t\t\t\t\t s->pipe_tc_be_rate_max);\n \ts->tc_ov_wm = s->tc_ov_wm_max;\n \ts->tc_ov_period_id = 0;\n \ts->tc_ov = 0;\n \ts->tc_ov_n = 0;\n \ts->tc_ov_rate = 0;\n+#endif\n \n \trte_sched_port_log_subport_config(port, subport_id);\n \n", "prefixes": [ "04/15" ] }