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GET /api/patches/57243/?format=api
{ "id": 57243, "url": "http://patches.dpdk.org/api/patches/57243/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1564404065-4823-2-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1564404065-4823-2-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1564404065-4823-2-git-send-email-viacheslavo@mellanox.com", "date": "2019-07-29T12:41:03", "name": "[1/3] net/mlx5: fix Tx completion descriptors fetching loop", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3eb95d7ccdd2298a2e9326fb5f056f77c056d6e3", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1564404065-4823-2-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 5812, "url": "http://patches.dpdk.org/api/series/5812/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5812", "date": "2019-07-29T12:41:02", "name": "net/mlx5: transmit datapath cumulative fix pack", "version": 1, "mbox": "http://patches.dpdk.org/series/5812/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57243/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57243/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 351261BF8D;\n\tMon, 29 Jul 2019 14:41:18 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 17F751BF79\n\tfor <dev@dpdk.org>; Mon, 29 Jul 2019 14:41:14 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tviacheslavo@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 29 Jul 2019 15:41:11 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n\t[10.210.17.40])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6TCfBRH010749;\n\tMon, 29 Jul 2019 15:41:11 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n\tby pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id\n\tx6TCfBw0005043; Mon, 29 Jul 2019 12:41:11 GMT", "(from viacheslavo@localhost)\n\tby pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id x6TCfBPB005042; \n\tMon, 29 Jul 2019 12:41:11 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n\tviacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "yskoh@mellanox.com, shahafs@mellanox.com", "Date": "Mon, 29 Jul 2019 12:41:03 +0000", "Message-Id": "<1564404065-4823-2-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1564404065-4823-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1564404065-4823-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 1/3] net/mlx5: fix Tx completion descriptors\n\tfetching loop", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch limits the amount of fetched and processed\ncompletion descriptors in one tx_burst routine call.\n\nThe completion processing involves the buffer freeing\nwhich may be time consuming and introduce the significant\nlatency, so limiting the amount of processed completions\nmitigates the latency issue.\n\nFixes: 18a1c20044c0 (\"net/mlx5: implement Tx burst template\")\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/net/mlx5/mlx5_defs.h | 7 +++++++\n drivers/net/mlx5/mlx5_rxtx.c | 46 +++++++++++++++++++++++++++++---------------\n 2 files changed, 38 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 8c118d5..461e916 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -37,6 +37,13 @@\n */\n #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)\n \n+/*\n+ * Maximal amount of normal completion CQEs\n+ * processed in one call of tx_burst() routine.\n+ */\n+#define MLX5_TX_COMP_MAX_CQE 2u\n+\n+\n /* Size of per-queue MR cache array for linear search. */\n #define MLX5_MR_CACHE_N 8\n \ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex 007df8f..c2b93c6 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -1992,13 +1992,13 @@ enum mlx5_txcmp_code {\n mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,\n \t\t\t unsigned int olx __rte_unused)\n {\n+\tunsigned int count = MLX5_TX_COMP_MAX_CQE;\n \tbool update = false;\n+\tuint16_t tail = txq->elts_tail;\n \tint ret;\n \n \tdo {\n-\t\tvolatile struct mlx5_wqe_cseg *cseg;\n \t\tvolatile struct mlx5_cqe *cqe;\n-\t\tuint16_t tail;\n \n \t\tcqe = &txq->cqes[txq->cq_ci & txq->cqe_m];\n \t\tret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);\n@@ -2006,19 +2006,21 @@ enum mlx5_txcmp_code {\n \t\t\tif (likely(ret != MLX5_CQE_STATUS_ERR)) {\n \t\t\t\t/* No new CQEs in completion queue. */\n \t\t\t\tassert(ret == MLX5_CQE_STATUS_HW_OWN);\n-\t\t\t\tif (likely(update)) {\n-\t\t\t\t\t/* Update the consumer index. */\n-\t\t\t\t\trte_compiler_barrier();\n-\t\t\t\t\t*txq->cq_db =\n-\t\t\t\t\t\trte_cpu_to_be_32(txq->cq_ci);\n-\t\t\t\t}\n-\t\t\t\treturn;\n+\t\t\t\tbreak;\n \t\t\t}\n \t\t\t/* Some error occurred, try to restart. */\n \t\t\trte_wmb();\n \t\t\ttail = mlx5_tx_error_cqe_handle\n \t\t\t\t(txq, (volatile struct mlx5_err_cqe *)cqe);\n+\t\t\tif (likely(tail != txq->elts_tail)) {\n+\t\t\t\tmlx5_tx_free_elts(txq, tail, olx);\n+\t\t\t\tassert(tail == txq->elts_tail);\n+\t\t\t}\n+\t\t\t/* Allow flushing all CQEs from the queue. */\n+\t\t\tcount = txq->cqe_s;\n \t\t} else {\n+\t\t\tvolatile struct mlx5_wqe_cseg *cseg;\n+\n \t\t\t/* Normal transmit completion. */\n \t\t\t++txq->cq_ci;\n \t\t\trte_cio_rmb();\n@@ -2031,13 +2033,27 @@ enum mlx5_txcmp_code {\n \t\tif (txq->cq_pi)\n \t\t\t--txq->cq_pi;\n #endif\n-\t\tif (likely(tail != txq->elts_tail)) {\n-\t\t\t/* Free data buffers from elts. */\n-\t\t\tmlx5_tx_free_elts(txq, tail, olx);\n-\t\t\tassert(tail == txq->elts_tail);\n-\t\t}\n \t\tupdate = true;\n-\t} while (true);\n+\t/*\n+\t * We have to restrict the amount of processed CQEs\n+\t * in one tx_burst routine call. The CQ may be large\n+\t * and many CQEs may be updated by the NIC in one\n+\t * transaction. Buffers freeing is time consuming,\n+\t * multiple iterations may introduce significant\n+\t * latency.\n+\t */\n+\t} while (--count);\n+\tif (likely(tail != txq->elts_tail)) {\n+\t\t/* Free data buffers from elts. */\n+\t\tmlx5_tx_free_elts(txq, tail, olx);\n+\t\tassert(tail == txq->elts_tail);\n+\t}\n+\tif (likely(update)) {\n+\t\t/* Update the consumer index. */\n+\t\trte_compiler_barrier();\n+\t\t*txq->cq_db =\n+\t\trte_cpu_to_be_32(txq->cq_ci);\n+\t}\n }\n \n /**\n", "prefixes": [ "1/3" ] }